应用笔记 5673

MAX5860/MAX5862 Usage and Configuration Guide

By: Shannon Horwitz

摘要 : This usage and configuration guide contains important information needed to properly configure the MAX5860 and the MAX5862, high-density downstream cable QAM modulator, digital upconverter (DUC), and RF digital-to-analog converter (RF-DAC) devices. This document supplements information found in the MAX5860 and the MAX5862 data sheets, covering such topics as calculation of the data input interface bandwidth, digital predistortion configuration, and printed circuit board layout considerations. Configuration scripts and setup examples for the MAX5860 and the MAX5862 are also covered.


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Table of Contents

General Configuration Notes

The order in which the configuration registers are programmed can make a significant difference in the operation of the MAX5860 and the MAX5862. The following general information must be observed for startup and configuration of the MAX5860 and the MAX5862.
  • RST_N should be applied to initialize the data path after connecting the power and the clocks. The devices are muted and all registers are cleared to default values after global reset is asserted.
  • JTRST_N should be tied in parallel with RST_N to reset the TAP controller to a safe state after each power-up.
  • The removal of RST_N triggers an internal state machine, which requires approximately 9600 DATACLK time periods to complete its load of internal configuration registers (approximately 9.6µs using 1.0GHz DATACLK). This state machine loads trim values for the LVDS output bias generators.
  • Check the global configuration register (address 0x001) bits [11:8] to obtain the device revision number.
  • The DPD is in bypass mode after reset. Bypass mode is when the DPD passes the input to the output unchanged due to all DPD gains being set to zero.
  • The factory default for the maximum channel capacity is in effect unless the UPGRADE_CAP register is written with the proper value. The UPGRADE_CAP register must be written any time the keys change. The soft upgrade registers 0x015 to 0x019 can be written in any order.
  • Based on one’s band plan, the desired 32-channel combiners must first be unmuted to enable upstream clocks in the associated 8-channel combiners and QAM channels. Once the 32-channel combiners are unmuted, registers (other than the QAM-channel registers) can be written in any order.
  • Based on one’s band plan, the individual QAM channels must first be unmuted to enable channel clocks to allow register configuration.
  • To remove any power from the channels as they are being configured, set the gain stages to zero prior to configuration.
  • Configure all data input interface registers starting with address 0x500.
  • Load registers for each channel’s KF/LF value and numerically controlled oscillator (NCO) control words. After writing each channel, the channel LD_KFLF and LD_FCW bits must be toggled.
  • If global phase alignment is required, set the global load bit (GLB) in each channel’s SYMIF register. After the local loads, set the global LD_KFLF and global LD_FCW bits (address 0x001). After each channel’s KF/LF value has loaded, but before setting the global load bit, the user must set LD_KFLF for each individual channel.
  • The remaining configuration registers can be written in any order.
  • If using pseudo-random binary sequence (PRBS), best results are achieved when the seeds are not sequential. See the PRBS Seeds and Operation section for information about choosing PRBS seeds.
  • Lowest standby power is achieved by holding RST_N low. When RST_N is low, the contents of the configuration registers are lost.
The following information about pin connections is also important for startup and configuration of the MAX5860 and the MAX5862.
  • TEST_N and MODE must always be held at logic 1 (1.8V).
  • RSETI is directly connected to ground.
  • VREF must be connected to ground with a 100pF capacitor. A capacitor with the metric code 0402 or 0603 is best.
  • VDDDLL must always be connected to 1.8V.
  • REFCLK input pins must be connected to ground.
  • DTO is in a high-impedance output state until enabled. A pullup resistor might be required to avoid a floating input.
  • A11 (VDD10) and P11 (GND) are directly connected to the silicon. These pins are recommended for use as 1.0V voltage sense and ground pins.
  • TDC must be connected to ground.
  • It is recommended that DATACLKP/N be connected to an LC resonator filter as suggested in the devices’ data sheets. These should not be connected to anything else.
  • DLLOFF must be connected to devices capable of toggling the signal after each power-up for proper DLL startup.

The SPI Command Interface

The MAX5860 and the MAX5862 registers are configured using the SPI interface. Without configuration of the internal registers, the MAX5860 and the MAX5862 are completely muted. Since the SDO pin is three-state except during reads, the SDO and SDI pins can optionally be tied together. All writes performed using SPI are to nonvolatile memory and must be reloaded after each power-up or reset. The order in which the configuration registers are programmed can make a significant difference in the operation of the MAX5860 and the MAX5862.
The DATACLK clock must be present for SPI programming and have a frequency of at least six times the SPI SCLK frequency. SS_N should be high for a minimum of one SCLK between SPI commands.

Power Management

Heat can be an issue for configurations with higher channel counts. The user must monitor the temperature of the internal junction diode (by using the MAX6642 temperature sensor or a similar device) and take steps to avoid the MAX5860 and the MAX5862 junction temperature from exceeding 110°C. Good airflow and a heatsink are recommended. See application note 5674, “MAX5860/MAX5862 Thermal Model Considerations” for additional information.
When muted, each of the 32-channel combiners has its clock disabled as well as the clocks for all earlier blocks that feed the combiners, thereby saving power. When the clocks are muted and the DATACLK is active, registers can be configured, but no load pulses can be initiated.
Channels are individually muted to save power. When muted, channel data path clocks are disabled. Channel register configuration can still be performed, and most existing information about channel configuration is not lost. However, the local LD_KFLF bit must be set in order to recalculate the channel symbol rate. After unmuting a preconfigured channel, a local FIFO clear should be performed.

Setting Maximum Channel Capacity

The MAX5860 can be purchased with factory-programmed maximum channel capacities of 32, 48, 64, 96, or 128. Contact your Maxim Integrated representative to discuss field scalability options from factory preset configurations as low as 8 QAM channels. The MAX5862 can be purchased with factory-programmed channel capacities of 8, 16, 24, or 32. The MAX5860 and the MAX5862 can also be downgraded to set a lower maximum channel capacity than the factory-programmed maximum channel capacity.
To field-upgrade the channel capacity of the MAX5860, the user must purchase an upgrade key from Maxim Integrated. The upgrade key is derived from the device’s 56-bit master key code (master key register [55:0] from addresses 0x010 through 0x013). Each MAX5860 has a unique internal master key. Upgrading or downgrading the MAX5860’s channel capacity must be done via SPI after each reset since the upgrade keys are loaded into nonvolatile memory in the MAX5860.
Suggested upgrade procedure (applicable for only the MAX5860):
  • Load the upgrade capacity register (address 0x015) with the upgrade capacity via SPI.
  • Load the upgrade key registers (addresses 0x016 through 0x019).
Suggested downgrade procedure (applicable for either the MAX5860 or the MAX5862):
  • Load the upgrade capacity register (address 0x015) with the downgrade capacity via SPI.
  • Load the downgrade key registers (all zeros for addresses 0x016 through 0x019).
Reading the KEY_STATUS register (address 0xA98) allows monitoring of the channel capacity status. Bit [4] is 1 when the upgrade key is valid. Bits [3:0] display the current maximum channel capacity in 8-channel increments.
0000 = 8 channels
0001 = 16 channels

1110 = 120 channels
1111 = 128 channels
The default value for the current channel capacity bits [3:0] is the factory-programmed channel capacity. The FACTORY_CAP register (address 0x014) bits [3:0] always contain the factory-programmed capacity value.
The UPGRADE_CAP register is used during Maxim factory testing. For most users, the UPGRADE_CAP register can be ignored since the KEY_STATUS register provides the information needed to monitor capacity. Once the keys are loaded and valid, the UPGRADE_CAP register (address 0x015) bits [3:0] show the upgraded channel capacity. Bit [12] indicates that the user has downgraded the capacity to a capacity lower than that programmed at the factory. DCAP [11:8] indicates the actual downgraded capacity value.
Loading the UPGRADE_CAP register (address 0x015) value triggers an internal state machine to allow the upgraded channel capacity value. Addresses 0x015 through 0x019 can be written in any order. The actual key validation is an asynchronous operation. After the upgrade capacity is loaded and the upgrade key load is complete, the upgraded capacity is available. If the keys and capacity do not match, the MAX5860 defaults back to the original factory-programmed channel capacity.

Integrated Digital-to-Analog Converter (DAC)

The MAX5860 and the MAX5862 have an integrated 14-bit, 4.6Gsps DAC. Since the DAC has a built-in DLL, the DLL in the DUC is not used.
The MAX5860 and the MAX5862 DPD provides correction for the (fDAC/2) - 2 × fOUT spur in the operation of the DAC.

Analog Output

The outputs need to be pulled up externally to VAVDD33. It is recommended that inductors be used for this purpose, as shown in Figure 1. The use of discrete inductors and capacitors allows for near perfect symmetry in the output circuit layout. An external 50Ω differential load is also required to avoid excessive voltage swings at the DAC output pins.
Figure 1. Typical output circuit.
Figure 1. Typical output circuit.

Clock Inputs

The DAC has a universal, differential clock input (CLKP, CLKN), which operates from a separate power supply (VAVCLK) to achieve the best possible jitter performance. The two clock inputs should be driven from a differential clock source. A sine wave or a square wave signal can be used.
For the highest speeds and highest performance, a sinusoidal clock should be used. At rates where it is feasible, a LVDS or PECL clock may also be utilized. The LVDS or PECL clock must be AC-coupled to the DAC clock inputs. Each pin is internally DC-biased to 1/3 the supply voltage VAVCLK. The clock input has an internal 100Ω differential termination resistor. For 50Ω (differential) termination at high clock frequencies, an additional external termination resistor is required between CLKP and CLKN. The balanced input should be AC-coupled unless the common-mode of the clock source is within the specifications for the MAX5860 and the MAX5862 CLKP/CLKN clock input. An example of a well-balanced, single-ended-to-differential application circuit using three baluns is shown in Figure 2.
Figure 2. Balanced clock interface circuit.
Figure 2. Balanced clock interface circuit.

Clock Duty Cycle

The MAX5860 and the MAX5862 DAC input clock is supplied at a frequency (fCLK) that is one-half the DAC update rate (fDAC). The DAC output updates on both edges of the clock. Deviation from a balanced duty cycle will contribute to images in the output spectrum. The magnitude of the images is dependent on the absolute value of the deviation from an ideal 50% duty cycle. These artifacts will occur at the following frequencies:
fIMAGE = (fDAC/2) ±fOUT (Eq. 1)
To minimize the image at fDAC/2 - fOUT, the clock duty cycle should be close to 50%. A filtered sine wave will have this characteristic. An offset voltage at the input of the clock input buffer will cause a duty-cycle change. The duty-cycle change in percentage is approximately:
(100/π) × VOFS/ampl (Eq. 2)
Where VOFS is the offset voltage and ampl is the peak clock input amplitude. With a clock amplitude of 1V peak (differential), an offset of 3.14mV would shift the duty cycle from 50.0% to 50.1%/49.9%.

Calculating the Data Input Interface Bandwidth and Port Interface Programming

Port Interface Considerations

Each QAM data channel in the MAX5860 and the MAX5862 can have its data sourced from either an internal PRBS (unique per channel) or from the multiplexed data at the input data interface. The MAX5860 has four ports of parallel interface and time slot-based architecture to provide data access for a maximum of 128 channels. The MAX5862 has a single port parallel interface and time slot-based architecture to provide data access for a maximum of 32 channels. The interface can be programmed for single-data rate (SDR) or double-data rate (DDR) mode. Refer to the MAX5860 data sheet or the MAX5862 data sheet for timing diagrams in each mode.
The MAX5860 interface provides complete flexibility to the user to configure any time slot of any of the four ports to any of the 128 channels. All four ports of the MAX5860 use the same clock for reference. The MAX5862 interface provides complete flexibility for the user to configure any time slot of the single port to any of the 32 channels. Only the rising edge of PCLK is used in SDR mode, whereas both the rising and falling edges of PCLK are used in DDR mode. The clock frequency of this interface is calculated based on the symbol rate and the number of maximum time slots used.
In SDR mode:
PCLK_freq ≥ (fastest symbol rate of any channel) × (# of time slots per port)
In DDR mode:
PCLK_freq ≥ (fastest symbol rate of any channel) × (# of time slots per port)/2
The maximum time slot value and the SDR/DDR modes are programmed using the register located at 0x500. All ports have the same number of time slots. Time slots can have a value ranging from 0 to 32 (DDR mode) or 0 to 16 (SDR mode). Assigning a channel to time slot 0 (default) provides an all zeros data condition to the channel input.

Symbol Rate

The symbol rate depends on each channel’s data source and can vary from 1 to 8MSym/s. The MAX5860 and the MAX5862 accept a master clock equal to fDATACLK = fDAC/4. This master clock is expected to be locked to 10.24MHz. The symbol rate fSYM is calculated in DOCSIS using a reference frequency of 10.24MHz and two arbitrary 16-bit integer numbers, M and N:
fSYM = 10.24 × M/N (Eq. 3)
The selection of M and N determines the exact symbol rate.
In the MAX5860 and the MAX5862, M and N are represented by 27-bit numbers LF and KF. Avoid an LF value equal to 2N, where N is the integer. If LF = 2N, a calculation error causes artifacts in the output spectrum. The symbol rate is calculated as:
fSYM = (KF/LF) × (fDATACLCK/128) = (KF/LF) × (fDAC/512) = 10.24 × (M/N)[MSym/s] (Eq. 4)
It is important to select fDAC so that LF and KF can adequately represent M and N.
See Table 1 for example M/N values and symbol rates.
Table 1. Example Symbol Rates
J.83 Annex Type Channel Bandwidth Modulation M N Symbol Rate (MSym/s)
B 6 64-QAM 401 812 5.056945
B 6 256-QAM 78 149 5.360536
A 8 64-QAM 869 1280 6.952
A 8 256-QAM 869 1280 6.952
C 6 64-QAM 1889 3643 5.309733
C 6 256-QAM 1889 3643 5.309733
Once the PCLK clock frequency is determined, each channel can be assigned a time slot and a port using the SYMIF registers (addresses 0x501 through 0x580). The channel must be unmuted for it to be active and accept configuration. If the user has unmuted the maximum permissible channels, additional channels cannot be unmuted. There are two FIFO reset bits in the SYMIF registers used to configure the method of resetting the FIFO associated with each channel: GBL_RST and LCL_RST. Each channel FIFO should be reset using the local reset bit, which clears the internal FIFO registers.
In the MAX5860 and the MAX5862, each channel feeds specific channel combiners and upsamplers (see Figure 3). Each 8-channel combiner, which contains a set of eight consecutive channels, has a maximum bandwidth of 48MHz. As a result, in an 8-channel combiner, the following example combinations are possible:
  • Eight 6MHz bandwidth signals
  • Six 6MHz bandwidth signals plus one 8MHz bandwidth signal
  • Six 8MHz bandwidth signals
Similarly, four 8-channel combiners combine to achieve the maximum 192MHz bandwidth of a 32-channel combiner. With a master clock frequency of fDATACLK = 1152MHz, the single-channel, 8-channel, and 32-channel bandwidths are 9MHz, 54MHz, and 216MHz, respectively.
When a channel is selected to be unmuted, the corresponding 32-channel combiner must be first unmuted (address 0x500). Channels 1 through 32 are part of the 32-channel combiner “_1”, channels 33 through 64 are part of the 32-channel combiner “_2”, etc. (see Figure 3).
Data interface programming is mandatory, even if PRBS is being used as the source for each channel. The channel should first be unmuted for further processing.
Figure 3. Channel and block-combiner numbering reference.
Figure 3. Channel and block-combiner numbering reference.

Programming the Channel Combiners: Setting Channel Parameters, Calculating Intermediate Frequency, Estimating Correct Gain Value

The next step is to configure each channel for its processing method. A channel should be configured for the correct QAM mapper, the excess bandwidth factor α in the root-raised cosine (RRC) filter, and the symbol rate (KF/LF). Also, the center frequency of each channel needs to be known in order to program the NCOs at different stages in the channel combining process. The gain of each channel needs to be adjusted in order to balance the power over all enabled channels.
Each channel can be configured to any QAM mode. Table 2 shows the 3 bits of binary value that must be programmed for each channel at 0x108, 0x10F, etc.






Table 2. QAM Mapper Settings
Selection Type Bus Bit Width Input Port Bus Partitioning MSB
000 TCM 256-QAM 8 Bits [7:4] are I
Bits [3:0] are Q
Bit 7 is MSB - I
Bit 3 is MSB - Q
001 TCM 64-QAM 6 Bits [5:3] are I
Bits [2:0] are Q
Bit 5 is MSB - I
Bit 2 is MSB - Q
010 Diff Grey 16-QAM 4 Bits [3:0] used Bit 3 is MSB
011 Diff Grey 32-QAM 5 Bits [4:0] used Bit 4 is MSB
100 Diff Grey 64-QAM 6 Bits [5:0] used Bit 5 is MSB
101 Diff Grey 128-QAM 7 Bits [6:0] used Bit 6 is MSB
110 Diff Grey 256-QAM 8 Bits [7:0] used Bit 7 is MSB
111 10-bit bypass mode with Offset register 10 Bits [9:5] are I
Bits [4:0] are Q
Bit 9 is MSB - I
Bit 4 is MSB - Q
The excess bandwidth (rolloff) factor for each channel can be programmed using the alpha value at the locations 0x108, 0x10F, etc. (Table 3). The same register can be used to enable the data source as internal PRBS by setting the PRBS enable bit.
Table 3. Alpha Selection
Alpha Selection (2-Bits Binary) Excess Bandwidth Factor J.83 Annex Type
00 0.12 B
01 0.13 C
10 0.15 A
11 0.18 B
The bandwidth of each channel can be controlled by setting the KF and LF values for each channel. The calculation of KF and LF depends on the DAC update rate and symbol rate for each channel. The DAC update rate is also related to the reference frequency of 10.24MHz in the following equations:
Z = fDAC/10.24MHz (Eq. 5)
KF/LF = (512 × M)/(N × Z) (Eq. 6)
Both KF and LF should be integer numbers with a maximum value of 224 - 1 and should not have any common multiplication factors. For example, if Z = 450 (which produces a fDAC of 4608MHz), M = 78, and N = 149, then the value KF/LF is calculated as:
KF/LF = (512 × 78)/(149 × 450) = 6656/11175 (Eq. 7)
The KF and LF values are 27 bits in width. The 24 LSBs of each KF/LF value are programmed in sets of three registers at addresses 0x109 through 0x10B, 0x110 through 0x112, etc. The 3 MSBs of each KF/LF value are programmed in the registers at addresses 0x104 through 0x106, 0x144 through 0x146, etc. for a group of 8 channels. Once a new value for KF/LF is loaded into the register for the corresponding channels, set the LD_KFLF bit of the SYMIF register (address 0x108, 0x10F, etc.) for each individual channel.
The center frequency of each channel is configured by setting the four NCOs involved in the channel combining process. Each channel goes through the four stages of the channel combining process. As a result, the four NCOs need to be configured to obtain the correct center frequency for each channel. There is a single NCO associated with each channel (128 in total), 16 NCOs for octal-channel combining, four NCOs for the block-level combining process, and a single NCO for block modulation across all 128 channels. Table 4 lists the resolution and control word width used to calculate the output frequency of each NCO.


Table 4. NCO Configuration
Type Frequency Resolution Size of Control Word (Bits) Output Frequency Range
NCO1 fDAC/(225) 19 ±fDAC/128
NCO2 fDAC/(225) 21 ±fDAC/32
NCO3 fDAC/(222) 20 ±fDAC/8
NCO4 fDAC/(222) 21 ±fDAC/4
Note: All control words should be written in a signed-magnitude format.
Many combinations can generate the same center frequency by using different intermediate frequencies. The methods used to assign the frequency to NCOs are outlined in sections Calculating the Frequency Control Word When Only One Channel Is Enabled and Calculating the Frequency Control Word When More Than One Channel Is Enabled.

Calculating the Frequency Control Word When Only One Channel Is Enabled

When calculating the frequency for an NCO output, one needs to consider that the entire channel is limited by the bandwidth. Assuming that fDAC = 4096Msps, the maximum bandwidths for the 1st, 2nd, and 3rd modulation stages are 48MHz, 192MHz, and 950MHz, respectively. For NCO1, the frequency must be within the range ±(0.5 × 48MHz - 0.5 × channel bandwidth). Similarly, for NCO2, the range is ±(0.5 × 192MHz - 0.5 × the combined bandwidth of 8 channels). For NCO3, the range is ±(0.5 × 950MHz - 0.5 × the combined bandwidth of 32 channels). The frequency of NCO4 is generally chosen to move the synthesized block from baseband to the desired RF frequency. The highest synthesized output frequency should be lower than fDAC/4.
For example, if the center frequency of a 6.0MHz channel is 150MHz and fDAC = 4096MHz, start with NCO1 = -21MHz, NCO2 = -72MHz, NCO3 = -288MHz, and NCO4 = 531MHz.
When calculating the NCO output frequency, the frequency difference due to the NCO output grid and the required frequency must be taken into account. The difference in frequency should be considered in the frequency calculations of the next stage.
The control word for the NCO output frequency can be calculated as:
CW = Freq/NCO_res (Eq. 8)
Truncate the fractional part.
Now calculate FNCO = CW × NCO_res. The difference between Freq and FNCO should be passed to the calculation in the next stage in order to match the final frequency as close as possible.

Calculating the Frequency Control Word When More Than One Channel Is Enabled

This process uses the band center frequency approach to determine the output frequency required for each NCO.
  1. Determine the center frequency of the entire band:
  2. FNCO4 = ((fcen_n + 0.5 × bw_n) + (fcen_1 - 0.5 × bw_1))/2 (Eq. 9)
    Where fcen_n and bw_n are the center frequency and bandwidth of the last channel, and fcen_1 and bw_1 are the center frequency and bandwidth of the first channel.
  3. Subtract the NCO4 frequency from the center frequency of each channel. Next, calculate the band center frequency for each group of channels that have a total bandwidth of 192MHz or a maximum of 32 channels. If all 128 channels are used, this calculation determines the required output frequency of the four NCO3s. If fewer channels are required, enable fewer NCO3s, depending upon the entire bandwidth used.
  4. The NCO3 frequencies are subtracted from the center frequency of each channel and fall in the same group (32 channels or less). This subtraction is performed on the center frequency received after the NCO4 frequency subtraction (step two). Also, the same method is used to find the frequency of each NCO2 by considering all 8 channels or channels with a total maximum of 48MHz bandwidth. The result is the output frequencies for 16 NCO2s.
  5. Subtract the output frequencies of these NCO2s from the corresponding center frequency of each channel belonging to the same group of 48MHz bandwidth. The result is the output frequencies for each NCO1.
These frequencies are used to calculate the control word for each NCO, which are programmed in their respective FCW bit fields in the MAX5860 and the MAX5862. Once these control words are loaded into the registers, they need to be loaded in the phase accumulator of each NCO by setting the corresponding LD_FCW bits. The MAX5860 and the MAX5862 feature an option to perform clock phase alignment for all NCOs simultaneously. Alignment is triggered by performing an SPI command to globally load the NCO counters. The global load register bits are self-clearing, which is activated by writing logic 1 to the global load control bit.
Table 5. NCO Control Registers
NCO Register Location Data Type
NCO1 0x10C through 0x10D, 0x113 through 0x114, etc. Nineteen bits of control value for each of the 128 channels of NCO1
NCO1 0x108, 0x10F, etc. LD_FCW bit for loading the NCO1 control word
NCO2 0x100 through 0x101, 0x140 through 0x141, etc. Twenty-one bits of control value for each of the 16 channels of NCO2
NCO2 0x100, 0x140, etc. LD_FCW bit for loading the NCO2 control word
NCO3 0x021 through 0x022, 0x029 through 0x02A, etc. Twenty bits of control value for each of the 4 channels of NCO3
NCO3 0x020, 0x028, etc. LD_FCW bit for loading the NCO3 control word
NCO4 0x042 through 0x043 Twenty-one bits of control value for NCO4
NCO4 0x043 LD_FCW bit for loading the NCO4 control word
All NCOs 0x001 LD_FCW bit for global loading

Optimizing Channel Power

For optimal performance, one of the most important settings in the MAX5860 and the MAX5862 involves balancing the power of each channel. The power contribution through each channel depends on the channel symbol sequence and the value of the carrier signal. If the gains are set too high, then saturation in the filters and other blocks can occur. If the gains are set too low, then the signal-to-noise ratio is degraded. The balancing of gains with respect to channel count can be seen in the G2 gain values. The G2 gain values change based on the number of active channels within the MAX5860 and the MAX5862 devices but are independent of modulation and QAM mapping selections. Table 6 shows the optimal gains for the Annex B, 256-QAM mapping mode. Multichannel configurations can be adjusted for optimal performance.
Table 6. Gain Settings for Annex B, 256-QAM
Number of Channels G1
11 Bits
G2
8 Bits
G3
8 Bits
G4
8 Bits
G5
8 Bits
1 0x28A 0xFE 0xFE 0xFE 0xFE
2 0x28A 0xA1 0xFE 0xFE 0xFE
4 0x28A 0x66 0xFE 0xFE 0xFE
8 0x28A 0x48 0xFE 0xFE 0xFE
16 0x28A 0x2D 0xFE 0xFE 0xFE
32 0x28A 0x20 0xFE 0xFE 0xFE
64 0x28A 0x14 0xFE 0xFE 0xFE
128 0x28A 0x0D 0xFE 0xFE 0xFE
Note: All gain values must be positive numbers. Only the magnitude bits are written to the respective registers.
Table 7 shows the appropriate settings for the G1, G3, G4, and G5 configuration bits. These settings are not affected by the channel count, but the G1 setting can be optimized based on the desired modulation and QAM mapping selection.
Table 7. Gain Settings Based on Modulation and QAM Mapping Selections
Annex B,
64-QAM
Annex B,
256-QAM
Annex C,
64-QAM
Annex C,
256-QAM
 
G1 = 0x2B9
G3 = 0xFE
G4 = 0xFE
G5 = 0xFE
G1 = 0x28A
G3 = 0xFE
G4 = 0xFE
G5 = 0xFE
G1 = 0x2B9
G3 = 0xFE
G4 = 0xFE
G5 = 0xFE
G1 = 0x28A
G3 = 0xFE
G4 = 0xFE
G5 = 0xFE
 
Annex A,
16-QAM
Annex A,
32-QAM
Annex A,
64-QAM
Annex A,
128-QAM
Annex A,
256-QAM
G1 = 0x32E
G3 = 0xFE
G4 = 0xFE
G5 = 0xFE
G1 = 0x49F
G3 = 0xFE
G4 = 0xFE
G5 = 0xFE
G1 = 0x2B9
G3 = 0xFE
G4 = 0xFE
G5 = 0xFE
G1 = 0x422
G3 = 0xFE
G4 = 0xFE
G5 = 0xFE
G1 = 0x28A
G3 = 0xFE
G4 = 0xFE
G5 = 0xFE

Spectral Inversion

The normal operation of the MAX5860 and the MAX5862 quadrature modulator is:
I × cos(ωt) - Q × sin(ωt) (Eq. 10)
Since cos(ωt) = cos(-ωt) and sin(ωt) = -sin(-ωt), spectral inversion can be achieved by inverting the Q-data as follows:
I × cos(ωt) - (-Q) × sin(ωt) = I × cos(-ωt) - Q × sin(-ωt) (Eq. 11)
Therefore, complementing the input bus Q-data inverts the output spectrum. It is also possible to invert the final RF output spectrum by configuring an inverted FCW for NCO4. This reorders the channels where channel 1 now becomes channel N, channel 2 now becomes channel N-1, etc. To place each channel in its original location, the input interface data should be sent to the time slots in the device in reverse order. This will correct for the intended center frequency.
If the internal QAM mapper is used, the individual channel spectrum cannot be inverted. If the internal QAM mapper is bypassed, the individual carriers can be spectrally inverted by externally complementing the Q-data for specific channels.

Power Monitor Configuration

The MAX5860 and the MAX5862 have the capability to monitor power levels at various stages in the processing. Refer to the MAX5860 data sheet or the MAX5862 data sheet for details on the location of power monitors.
The timer value should be configured as a 48-bit field, a threshold value in two’s complement data format to compare to the power level, and a mode bit to set the positive or negative power level to be monitored. If positive peaks need to be monitored, the user must set a positive threshold (and the MODE bit 1 of the PWRMON_CFG register) at the register address 0x046. If negative peaks need to be monitored, the user must set a negative value (and a MODE value of 0). The timer value can be programmed at the register addresses 0x047 through 0x049. Time lapsed is 64/fDAC (i.e., 16x the DATACLK period) × the timer value.
Once the timer value, threshold level, mode, and enable bit are set, a 1 written to the reset bit at 0x046 starts the monitoring process. When the programmed time period expires, an interrupt is generated, if enabled. All accumulators saturate to their maximum value.

Digital Predistortion (DPD) Configuration

The digital predistortion (DPD) block is the final processing stage in the MAX5860 and the MAX5862 data path. The DPD is always in the data path; however, setting the DPD gain stages (G1 through G10) to zero in the compensation branch of the individual DPD causes the DPD to pass the input to the output without modification. In relative terms, the DPD is considered bypassed when all DPD gains are zero. The DPD gain stage identifiers repeat some of the same gain stage names that are used by other gain stages in the data path. For example, DPD G1 is separate from channel G1.

Register Usage

There is a special gain for data ports B and D (i.e., the functional bypass mode). To enable the bypass mode, set register 0x081 bit 0 to logic 1 and set the DPD gain stage G2 (0x086) to a nonzero value. If 0x081 bit 0 is asserted logic 1 and gain register G2 is set to zero, then the register is not making any contribution and is in bypass mode.
If fDAC/2 - 3fOUT compensation is desired, DPD gain registers G3 (0x087) and G4 (0x088) are set to nonzero values. If registers G3 and G4 are zero, then the fDAC/2 - 3fOUT compensation output is zero. The user can also change the Delay 1 (0x082) and Delay 2 (0x083) settings, which default to 1 and 12, respectively. Delay 1 affects the upper path of fDAC/2 - 3fOUT compensation, and Delay 2 affects the lower path of fDAC /2 - 3fOUT compensation. Gain stage G3 affects the upper path of fDAC/2 - 3fOUT compensation, and gain stage G4 affects the lower path of fDAC/2 - 3fOUT. By default, odd-numbered samples are processed in the upper path. To change this so that even-numbered samples are processed in the upper path, set bit 1 of register 0x081 to logic 1. The range is ±1/512.
If DAC interleaving-error compensation is desired, DPD gain registers G1 (0x085) and G2 (0x086) are set to nonzero values. Each gain stage has a resolution of 12 bits. If gain stages G1 and G2 are zero, then the DAC interleaving-error compensation is zero. Gain stage G1 affects the upper path in DAC interleaving-error compensation, and gain stage G2 affects the lower path in DAC interleaving-error compensation. To work properly, the value of gain G2 should be nonzero, even in DPD functional bypass mode. The range is ±1/8.
If third-harmonic distortion (HD3) compensation is desired, DPD gain registers G5 (0x089) and G6 (0x08A) are programmed to nonzero values. Each gain stage has a resolution of 12 bits. If gain stages G5 and G6 are zero, then the HD3 compensation output is zero. Gain stage G5 affects the upper path of the HD3, and gain stage G6 affects the lower path of the HD3. The range is ±1/32.
If second-harmonic distortion (HD2) compensation is desired, DPD gain registers G7 (0x08B) and G8 (0x08C) are programmed to nonzero values. Each gain stage has a resolution of 12 bits. If gain stages G7 and G8 are zero, then the HD2 compensation output is zero. Gain stage G7 affects the upper path of the HD2, and gain stage G8 affects the lower path of the HD2. The range is ±1/32.
If fDAC/2 - 2fOUT compensation in the DAC is desired, DPD gain registers G9 (0x08D) and G10 (0x08E) are set to nonzero values. Each gain stage has a resolution of 8 bits. If gain stages G9 and G10 are zero, then the contribution from the fDAC/2 - 2fOUT compensation is zero. To bypass the prefilter in the fDAC/2 - 2fOUT path, bit 4 of register 0x081 is set to 1. The prefilter is not bypassed by default.
The user has the option to assign magnitude signs to the parallel outputs. If the sign bit (bit 5 of register 0x081) is zero, the -ve sign is attached to the outputs going to ports A and C and the +ve sign is attached to the outputs going to ports B and D. If the sign bit is logic 1, the -ve sign is attached to the outputs going to ports B and D and the +ve sign is attached to the outputs going to ports A and C. The range is ±1/32.
Delay 3 (0x084) can be programmed with a range of 0 to 9. Any value written to this register that is greater than nine is set to nine by default. There are six register delays added before Delay 3 as part of the DAC interleaving-error compensation. When Delay 3 reaches nine, the sum of the delays of the interleaving-error compensation path add up to 15, which is the maximum delay.

Digital Predistortion (DPD) Latency Contribution

The DPD has a deterministic latency of 119 + #delay3 (i.e., 112 + #delay3 + 6 + 1), where #delay3 is the value written to the DPD Delay 3 register with a range of 0 to 9. Register configuration in the DPD affects the total latency of the MAX5860 and the MAX5862. The DPD has a total latency of 14 clock cycles. All paths are delayed, which makes the default latency delay 14 cycles or 112 samples. There is a variable latency depending on register Delay 3. By default, #delay3 = 6, so the first sample is delayed by #delay3 + 6 + 1 = 13 samples plus the fixed 112 samples for a total of 125 sample delay. If #delay3 = 0, the first sample is delayed by 112 + 6 + 1 = 119 samples. In DPD bypass mode, the latency is 14 fixed clock cycles and one variable sample delay (i.e., a delay of 112 + 1 = 113 samples). In general, whenever the DPD is operational, there is a latency of 125 samples (i.e., 112 + #delay3 + 6 + 1).
Remember that as gain adjustments are made via register writes, the compensation effects observable on the MAX5860 and the MAX5862 outputs are delayed by the same associated latency.

Interrupts

The user can enable interrupt generation for various events on the MAX5860 and the MAX5862. This can be done by setting the appropriate interrupt enable bit in the register address 0x581.
Once an interrupt is generated, the user reads the interrupt control register (address 0x581) to check the source of the interrupt. The lower seven bits in this register indicate which type of interrupt has occurred. In case of a FIFO overflow/underflow interrupt, the user reads additional registers located at addresses 0x582 through 0x592 to pinpoint the interrupting FIFO of a particular channel.

Printed Circuit Board (PCB) Layout Considerations

Power-Supply Considerations

Grounding and power-supply decoupling can strongly influence the performance of the MAX5860 and the MAX5862. Unwanted digital crosstalk can couple through the input, reference, power-supply, and ground connections, thereby affecting dynamic performance. Proper grounding and power-supply decoupling guidelines for high-speed, high-frequency applications should be closely followed. This reduces EMI and internal crosstalk that can significantly affect dynamic performance.
Use of a multilayer PCB with separate ground and power-supply planes is required. Each power-supply input should at least be decoupled with a separate 0.047µF capacitor as close to the input as possible. Also, to minimize loop inductance, their opposite ends should have the shortest possible connection to the corresponding ground plane. Additionally, all power-supply voltages should be decoupled with tantalum or electrolytic capacitors at the point where they enter the PCB. Ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance.
It is recommended that the analog output and the clock input are run as controlled-impedance microstrip lines on the top layer of the board, directly above a ground plane, and that no vias are used for the clock input (CLKP, CLKN) or the analog output (OUTP, OUTN) signals. Depending on the length of the traces and the operating conditions, a low-loss dielectric material (such as ROGERS RO4003) as the top layer dielectric may be advisable.
The MAX5860EVKIT schematic and layout files can be used as a reference.

Thermal Considerations

When using the maximum capability of the MAX5860 and the MAX5862, significant heat might be generated. See application note 5674, “MAX5860/MAX5862 Thermal Model Considerations” for additional information. It is desirable to design the PCB to conduct heat away from the MAX5860 and the MAX5862. Adequate distance should be maintained between the MAX5860 or the MAX5862 and any other major heat source. Power and ground supplies should be positioned on the outer layers of the PCB stack to best dissipate heat.

DAC Output Coupling

The differential voltage between OUTP and OUTN can be converted to a single-ended voltage using a transformer or a differential amplifier configuration. The DAC outputs should be pulled up to VAVDD33. It is recommended to use bias tees built from discrete inductors and capacitors for the pullups. Two recommended output circuit configurations are shown in Figure 4. To achieve the maximum bandwidth, minimize the inductance in the ground lead on the secondary side of the transformer. Use a very short trace and multiple vias for the connection to the ground plane.
Figure 4. Balun transformer output (a) and amplified output configuration (b).
Figure 4. Balun transformer output (a) and amplified output configuration (b).

CMOS Signal Routing

The CMOS input signals should be routed as 50Ω transmission lines. Use 47Ω series load termination resistors at the MAX5860 and the MAX5862 package for the data input buses A, B, C, and D and for signals VALID, PCLK, PSYNC, MODE, and MODE2. The source FPGA outputs should be programmed with internal series source termination resistors of 50Ω. Series termination resistors might also be appropriate on the output signals RDYA-RDYD, RDYCLK, and RDYSYNC.
Tightly grouping the timing skews for the CMOS input signals is recommended. The AC Electrical Characteristics table in the MAX5860 data sheet and the MAX5862 data sheet shows a 1ns setup and a 1ns hold requirement. If the input is configured for 100MHz DDR, there are only 5ns between the clock edges. To allow for a sufficient timing margin, delay the PCLK by 3/4 phase.
RDYCLK is provided in the MAX5860 and the MAX5862 in order to guarantee capture of the FIFO-ready signals. The RDYCLK should be delayed by approximately 1/4 phase in order to position it properly with respect to the FIFO DATA VALID signals.

OEM Test Mode

The OEM_TEST function (address 0x003) unlocks all 128 channels for full-bandwidth testing. It allows up to 128 QAM channels to be driven by individual channel PRBS generators, or from a time slot on a designated port, by limiting the channel address range to one of eight contiguous slots.
Data transfer from individual port time slots can be tested. Time slot addressing is limited to eight contiguous slots at a time from one port at a time. External data can be directed to any QAM channel (or to multiple QAM channels) but only from one of the eight enabled time slots from the one selected port. If the data from the time slots is sent to multiple channels (>> 8), the user should take care to adjust gains to avoid the possibility of saturation.
CW[3:0]: Control word. Set to 1101 to enable OEM_TEST function. Any other data in CW[3:0] disables this test function.
PORT[1:0]: Select port:
00 = Port A
01 = Port B
10 = Port C
11 = Port D
SGRP[1:0]: Select a group of eight contiguous time slots:
00 = Time slots 1–8
01 = Time slots 9–16
10 = Time slots 17–24
11 = Time slots 25–32

PRBS Seeds and Operation

Each channel has its own unique PRBS generator for creating FEC-encoded data (symbols). The PRBS feature can be used to test the configuration and RF-performance of the MAX5860 and MAX5862 devices without using an external FEC-encoded data source (e.g., FPGA). In picking a seed, the user only needs to set the four d1_delay select bits (SYMIF register, one per channel) and the 8 bits of the appropriate seed value (SEEDA or SEEDB in the PRBS register), which combine to form a unique value for each channel. During PRBS operation, the d1_delay function is not operational.
PRBS seeds should not be assigned consecutive values per channel. The optimal situation would be to select the 12-bit seeds to be evenly spaced within the possible range of values (0 to 4095).
PRBS generators can be globally synchronized, if desired. Set the self-clearing global load bit via SPI, or use the MODE2 pin, to align all generated PRBS.
As a side note, port control signals can toggle during PRBS operation. This includes cases where all unmuted channels are being sourced with PRBS data. These toggles will be ignored.

Configuration Setup Examples for the MAX5860 and the MAX5862

Configuration Scripts

Users of the MAX5860 and the MAX5862 can obtain Perl programs (gen_inp_cfg.pl and gen_spi_cmd.pl) from their Maxim Integrated representative to assist with configuration-related tasks. These programs can be used to create an initial setup command file that is loaded to the registers via SPI. The user creates an input text file to describe all setup-related requirements. The Perl programs perform all expected parameter checks and internally calculate the KF/LF, the NCO control word, the gains, and the other values.
The gen_inp_cfg and gen_spi_cmd files are very high level definition and lower level definition files, respectively. The user can start at the very high level of the gen_inp_cfg Perl file, as shown in the Command Line Call Examples for Higher Level Definition section. Or the user can start with low-level programming as discussed in the Setup Examples for Lower Level Definition section.
The input parameters for the gen_inp_cfg Perl script are basic, generating a simple configuration of the defined channel count, the QAM mapping, the center frequency, and the data rate.
An example call to gen_inp_cfg is as follows:
gen_inp_cfg.pl -NOC 1 -ANNEX B -QAM 256 -DDR -PRBS -MAX_TS 2 -Z 450 -BCF 600e6 -OPF 001SB256_5860_PRBS_4608M_600M_cfgen.txt
The previous call would set up a configuration for (1) Annex B, 256-QAM channel of internal PRBS data with fDAC = 4608MHz and fOUT = 600MHz. It would place this setup information into the file called 001SB256_5860_PRBS_4608M_600M_cfgen.txt.
The gen_inp_cfg program has these command line options:
  • NOC <number of channels>: A value of 1 (min) to 128 (max)
  • ANNEX <A/B/C>: To select the correct BW and alpha, based on the QAM mapper mode
  • QAM <16/32/64/128/256>: To select the correct QAM, internally differentiate between TCM and Grey
  • SDR: To use the SDR mode of the data input interface
  • DDR: To use the DDR mode of the data input interface
  • MAX_TS <slot count>: 1- 16/32 in the case of the SDR/DDR modes
  • PRBS: To use the internal PRBS as the input symbol source, default seeds are used. The user can change them and regenerate the SPI command file.
  • Z <integer number>: To calculate the fDAC where fDAC = 10.24MHz × Z
  • BCF <center frequency of the entire band>: This must be supplied in Hz. The default is BCF = 600e6.
  • M and N <value>: To define the symbol rate as defined in the MAX5860 data sheet
  • OPF <filename>: To generate the output file with name specified
The resultant output of the gen_inp_cfg Perl script command is a file that is the input file for the gen_spi_cmd Perl script.
An example call to the gen_spi_cmd is as follows:
gen_spi_cmd.pl test/cfgfiles/001DB256_5860_PRBS_4608M_600M_cfgen.txt > 001DB256_5860_PRBS_4608M_600M.txt
The output file 001DB256_5860_PRBS_4608M_600M.txt is the register load file which configures the MAX5860 registers.

Setup Examples for Lower Level Definition

In the following examples, fDAC is 4608MHz.
  1. Configure the MAX5860 and the MAX5862 for a single J.83 Annex B, 6MHz channel, with TCM 256-QAM mapping and a center frequency of channel of 600MHz.
  2. #File contains the MAX5860 configuration data.
    #------------------------------------------------------
    #Set the verbose variable to display the detailed error messages.
    verbose=Yes
    
    #fdac=Z*fref
    fref=10.24
    fdac_z=450
    
    #Input demux configuration 
    #maximum no. of time slots for each port.
    max_ts=5
    
    #SDR mode=1, DDR mode=0
    sdr=Yes
    
    #Set this to Yes if you want to provide M and N values instead of KF and 
    #LF values. Then program internally calculates the KF and LF values.
    cal_KFLF=Yes 
    
    #If Yes, calculates NCO1/NCO2/NCO3/NCO4 output from center freq of each #channel.
    cal_nco_fo=Yes
    
    #If Yes, calculates control word for each NCO.
    cal_cws=Yes
    
    CFG_CH
    #Each channel's configuration
    #Note: Don’t leave any column blank. Add at least a default value. 
    #
    #Total 18 columns
    #ChID PID TsID GFIFORST QAM QOFF ALPHA KF LF F1 GLB_KF LD_KF LD_FCW G1 G2 D1 D2 BW
    1 0 1 0 0 0 0.12 78 149 6.0e+08 0 1 1 0 0 0 0 6e+06
    
    In the last two lines of code above, the data in the first three columns defines the channel ID, the port ID assigned to this channel, and the time slot for the data input interface. The data in the fifth column defines the QAM mapper mode (i.e., 256, 128, 64, 32). The data in the sixth column is the QAM mapper offset, if a bypass mode is used. The data in the seventh column is the rolloff factor. The data in the eighth and ninth columns define the KF/LF and M/N values, respectively. (Interpretation depends on the cal_KFLF settings. If cal_KFLF=Yes, then the user should use M/N values.) The data in the tenth column defines the center frequency of channel. The data in the last column defines its bandwidth. The data in columns eleven through seventeen (i.e., GLB_KF through D2) can be left as shown. G1 and G2 are calculated internally based on the enabled channels. This line of code can be copied multiple times with different settings for additional channels.
    CFG_8CC
    #Define the configuration for each 8-channel combiner block.
    #8CCID,F2,LD_FCW,G3
    1 0 1 0 
    
    CFG_32CC
    #Define the configuration for each 32-channel combiner block.
    #32CCID,F3,LD_FCW,G4
    1 0 1 0 
    
    CFG_128CC
    #Define the configuration for each 128-channel combiner block.
    #128CCID,F4,LD_FCW,G5
    1 0 1 0
    
    All FCW gain values are calculated internally. Therefore, the definitions under the 8-, 32 , and 128-channel combiners (i.e., CFG_8CC, CFG_32CC, CFG_128CC) can be left as is. However, the user has to add sufficient definition lines, based on the requirements of additional channels.
    CFG_PRBS
    #PRBS as source for channels
    #ChID,SEED
    1 3713
    
    #XOR/SYNC
    #Set xor_en to Yes if XORing of the output data with the LFSR is #needed.
    xor_en=NO
    
    #Select the TAP for LFSR. It’s a 16-bit register where only 2 bits are
    #set at any point of time.
    xor_tap=12
    
    #Set sync_en to Yes if LFSR data is needed on the SYNC pin.
    sync_en=Yes
    
    #Select the TAP for LFSR. It’s a 16-bit register where only 2 bits are
    #set at any point of time.
    sync_tap=10
    
    CFG_PWR_MON
    #Power monitor configuration
    pm_en=NO
    pm_thrs=200
    pm_mde=0
    pm_count=54321987500
    
    CFG_INT
    #Interrupt settings
    en_intrp=Yes
    en_int_pmon=NO
    en_int_otest=NO
    en_int_ofifo=NO
    en_int_ufifo=NO
    en_int_cap=NO
    
    CFG_DPD
    #The following variables configure the DPD block.
    dpd_by_pass=Yes
    dpd_dac_even_sam=NO
    dpd_bd_off=NO
    dpd_ac_off=NO
    dpd_d1=0
    dpd_d2=0
    dpd_d3=0
    
    #General configuration
    #Program the required delay value.
    gbl_d6=No
    gbl_d5=No
    gbl_d4=No
    gbl_d3=No
    
  3. Configure the MAX5860 and the MAX5862 for a single J.83 Annex B, 6MHz channel, with TCM 64-QAM mapping and a center frequency of channel of 600MHz.
  4. Only the coding that differs from the first section is listed below.
    The data in the fifth column, for the QAM mapper mode, changed to TCM 64 (1). The data in the seventh column, for the rolloff factor (i.e., alpha), changed to 0.18. The data in the eighth and ninth columns changed to M=401 and N=812, respectively.
    CFG_CH
    #Each channel's configuration
    #ChID PID TsID GFIFORST QAM QOFF ALPHA KF LF F1 GLB_KF LD_KF LD_FCW G1 G2 D1 D2 BW
    1 0 1 0 1 0 0.18 401 812 6.0e+08 0 1 1 0 0 0 0 6e+06
    
  5. Configure the MAX5860 and the MAX5862 for a single J.83 Annex A, 8MHz channel, with Grey 256-QAM mapping and a center frequency of channel of 237MHz.
  6. Only the coding that differs from the first section is listed below.
    The data in the fifth column, for the QAM mapper mode, changed to Grey 256 (6). The data in the seventh column, for the rolloff factor, changed to 0.15. The data in the eighth and ninth columns changed to M=869 and N=1280, respectively. The center frequency of channel in the tenth column changed to 537MHz, and the bandwidth in the eighteenth column changed to 8MHz.
    CFG_CH
    #Each channel's configuration
    #ChID PID TsID GFIFORST QAM QOFF ALPHA KF LF F1 GLB_KF LD_KF LD_FCW G1 G2 D1 D2 BW
    1 0 1 0 6 0 0.15 869 1280 5.37e+08 0 1 1 0 0 0 0 8e+06
    
  7. Configure the MAX5860 and the MAX5862 for four J.83 Annex C, 6MHz channel, with Grey 256-QAM mapping and a center frequency of band of 600MHz.
  8. Only the coding that differs from the first section is listed below.
    Both the channel ID in the first column and the time slots in the third column are assigned 1 to 4. The data in the fifth column, for the QAM mapper mode, changed to Grey 256 (6). The data in the seventh column, for the rolloff factor, changed to 0.13. The data in the eighth and ninth columns changed to M=1889 and N=3643, respectively. The center frequencies of channels in the tenth column changed to 591MHz, 597MHz, 603MHz, and 609MHz, and the bandwidths of the channels in the eighteenth column changed to 6MHz.
    CFG_CH
    #Each channel's configuration
    #ChID PID TsID GFIFORST QAM QOFF ALPHA KF LF F1 GLB_KF LD_KF LD_FCW G1 G2 D1 D2 BW
    1 0 1 0 6 0 0.13 1889 3643 5.91e+08 0 1 1 0 0 0 0 6e+06
    2 0 2 0 6 0 0.13 1889 3643 5.97e+08 0 1 1 0 0 0 0 6e+06
    3 0 3 0 6 0 0.13 1889 3643 6.03e+08 0 1 1 0 0 0 0 6e+06
    4 0 4 0 6 0 0.13 1889 3643 6.09e+08 0 1 1 0 0 0 0 6e+06
    
  9. Configure the MAX5860 and the MAX5862 for twelve J.83 Annex A, 8MHz channel, with Grey 128-QAM mapping and a center frequency of entire band of 600MHz.
  10. Only the coding that differs from the first section is listed below.
    Because the number of channels per port is 12, the maximum slot value has changed to 12.
    max_ts=12
    
    The channel ID in the first column is assigned 1 to 6 and 9 to 14, because the maximum bandwidth for each 8-channel combiner is limited to 48MHz. The time slots in the third column are contiguous from 1 to 12.
    CFG_CH
    #ChID PID TsID GFIFORST QAM QOFF ALPHA KF LF F1 GLB_KF LD_KF LD_FCW G1 G2 D1 D2 BW
    1 0 1 0 5 0 0.15 869 1280 5.56000e+08 0 1 1 0 0 0 0 8e+06 
    2 0 2 0 5 0 0.15 869 1280 5.64000e+08 0 1 1 0 0 0 0 8e+06 
    3 0 3 0 5 0 0.15 869 1280 5.72000e+08 0 1 1 0 0 0 0 8e+06 
    4 0 4 0 5 0 0.15 869 1280 5.80000e+08 0 1 1 0 0 0 0 8e+06 
    5 0 5 0 5 0 0.15 869 1280 5.88000e+08 0 1 1 0 0 0 0 8e+06 
    6 0 6 0 5 0 0.15 869 1280 5.96000e+08 0 1 1 0 0 0 0 8e+06 
    9 0 7 0 5 0 0.15 869 1280 6.04000e+08 0 1 1 0 0 0 0 8e+06 
    10 0 8 0 5 0 0.15 869 1280 6.12000e+08 0 1 1 0 0 0 0 8e+06 
    11 0 9 0 5 0 0.15 869 1280 6.20000e+08 0 1 1 0 0 0 0 8e+06 
    12 0 10 0 5 0 0.15 869 1280 6.28000e+08 0 1 1 0 0 0 0 8e+06 
    13 0 11 0 5 0 0.15 869 1280 6.36000e+08 0 1 1 0 0 0 0 8e+06 
    14 0 12 0 5 0 0.15 869 1280 6.44000e+08 0 1 1 0 0 0 0 8e+06
    
    The number of 8-channel combiners increased from 1 to 2.
    CFG_8CC
    #8CCID,F2,LD_FCW,G3
    1 0 1 0 
    2 0 1 0
    
    Twelve PRBS are enabled, corresponding to the same number of channel IDs.
    CFG_PRBS
    #ChID,SEED
    1 3713
    2 1545
    3 1635
    4 2829
    5 2445
    6 1125
    9 530
    10 769
    11 3341
    12 374
    13 3389
    14 2029
    
  11. Configure the MAX5860 for 128 J.83 Annex C, 6MHz channel, with Grey 256-QAM mapping and a center frequency of channel of 600MHz.
  12. Only the coding that differs from the first section is listed below.
    Because the number of channels is 32 per port, the maximum slot value is 32.
    max_ts=32
    
    The data input interface mode is set to DDR.
    sdr=No
    
    All 128 channels are assigned different time slots and different ports.
    CFG_CH
    #ChID PID TsID GFIFORST QAM QOFF ALPHA KF LF F1 GLB_KF LD_KF LD_FCW G1 G2 D1 D2 BW
    1  0 1 0 6 0 0.13 1889 3643 2.19000e+08 0 1 1 0 0 0 0 6e+06 
    2  0 2 0 6 0 0.13 1889 3643 2.25000e+08 0 1 1 0 0 0 0 6e+06 
    . 3 29 0 6 0 0.13 1889 3643 9.63000e+08 0 1 1 0 0 0 0 6e+06 
    . 3 30 0 6 0 0.13 1889 3643 9.69000e+08 0 1 1 0 0 0 0 6e+06 
    . 3 31 0 6 0 0.13 1889 3643 9.75000e+08 0 1 1 0 0 0 0 6e+06 
    128 3 32 0 6 0 0.13 1889 3643 9.81000e+08 0 1 1 0 0 0 0 6e+06 
    
    All 16 8-channel combiners are enabled.
    CFG_8CC
    #8CCID,F2,LD_FCW,G3
    1 0 1 0 
    2 0 1 0 
    3 0 1 0 
    4 0 1 0 
    5 0 1 0 
    6 0 1 0 
    7 0 1 0 
    8 0 1 0 
    9 0 1 0 
    10 0 1 0 
    11 0 1 0 
    12 0 1 0 
    13 0 1 0 
    14 0 1 0 
    15 0 1 0 
    16 0 1 0 
    
    All four 32-channel combiners are enabled.
    CFG_32CC
    #32CCID,F3,LD_FCW,G4
    1 0 1 0 
    2 0 1 0 
    3 0 1 0 
    4 0 1 0
    
    All 128 PRBS sources are enabled.
    CFG_PRBS
    #ChID,SEED
    1 3713
    . 1545
    . 1635
    . 2829
    128 3280
    
To quickly create some of the input test files, the user can use the program gen_inp_cfg.pl as noted above. Some examples of command line options and file names are listed below.

Command Line Call Examples for Higher Level Definition

The following sections provide examples to call the gen_inp_cfg Perl script for a variety of configurations.

Annex B, 256-QAM

The following examples are for Annex B, 256-QAM mapped channels with fDAC = 4608MHz, fOUT = 500MHz, and DDR. These mapped channels use internal PRBS data and have channel counts ranging from 1 to 128.
gen_inp_cfg.pl -NOC 1 -ANNEX B -QAM 256 -DDR -PRBS -MAX_TS 5 -Z 450 –BCF 5e8
gen_inp_cfg.pl -NOC 2 -ANNEX B -QAM 256 -DDR -PRBS -MAX_TS 5 -Z 450 –BCF 5e8
gen_inp_cfg.pl -NOC 4 -ANNEX B -QAM 256 -DDR -PRBS -MAX_TS 7 -Z 450 –BCF 5e8
gen_inp_cfg.pl -NOC 8 -ANNEX B -QAM 256 -DDR -PRBS -MAX_TS 11 -Z 450 –BCF 5e8
gen_inp_cfg.pl -NOC 16 -ANNEX B -QAM 256 -DDR -PRBS -MAX_TS 16 -Z 450 –BCF 5e8
gen_inp_cfg.pl -NOC 32 -ANNEX B -QAM 256 -DDR -PRBS -MAX_TS 32 -Z 450 –BCF 5e8
gen_inp_cfg.pl -NOC 64 -ANNEX B -QAM 256 -DDR -PRBS -MAX_TS 32 -Z 450 –BCF 5e8
gen_inp_cfg.pl -NOC 128 -ANNEX B -QAM 256 -DDR -PRBS -MAX_TS 32 -Z 450 –BCF 5e8

Annex B, 64-QAM

The following examples are for Annex B, 64-QAM mapped channels with fDAC = 4608MHz, fOUT = 600MHz, and DDR. These mapped channels use internal PRBS data and have channel counts ranging from 1 to 128.
gen_inp_cfg.pl -NOC 1 -ANNEX B -QAM 64 -DDR -PRBS -MAX_TS 5 -Z 450 -M 401 -N 812 –BCF 600e6
gen_inp_cfg.pl -NOC 2 -ANNEX B -QAM 64 -DDR -PRBS -MAX_TS 5 -Z 450 -M 401 -N 812 –BCF 600e6
gen_inp_cfg.pl -NOC 4 -ANNEX B -QAM 64 -DDR -PRBS -MAX_TS 7 -Z 450 -M 401 -N 812 –BCF 600e6
gen_inp_cfg.pl -NOC 8 -ANNEX B -QAM 64 -DDR -PRBS -MAX_TS 11 -Z 450 -M 401 -N 812 –BCF 600e6
gen_inp_cfg.pl -NOC 16 -ANNEX B -QAM 64 -DDR -PRBS -MAX_TS 16 -Z 450 -M 401 -N 812 –BCF 600e6
gen_inp_cfg.pl -NOC 32 -ANNEX B -QAM 64 -DDR -PRBS -MAX_TS 32 -Z 450 -M 401 -N 812 –BCF 600e6
gen_inp_cfg.pl -NOC 64 -ANNEX B -QAM 64 -DDR -PRBS -MAX_TS 32 -Z 450 -M 401 -N 812 –BCF 600e6
gen_inp_cfg.pl -NOC 128 -ANNEX B -QAM 64 -DDR -PRBS -MAX_TS 32 -Z 450 -M 401 -N 812 –BCF 600e6

Annex A

The following examples are for Annex A, 156-QAM, 16-QAM, 32-QAM, 64-QAM, and 128-QAM mapped channels with fDAC = 4608MHz, fOUT = 600MHz, and DDR. These mapped channels use internal PRBS data and have channel counts ranging from 1 to 96.
gen_inp_cfg.pl -NOC 1 -ANNEX A -QAM 256 -DDR -PRBS -MAX_TS 5 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 2 -ANNEX A -QAM 256 -DDR -PRBS -MAX_TS 5 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 4 -ANNEX A -QAM 256 -DDR -PRBS -MAX_TS 7 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 6 -ANNEX A -QAM 256 -DDR -PRBS -MAX_TS 11 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 12 -ANNEX A -QAM 256 -DDR -PRBS -MAX_TS 12 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 24 -ANNEX A -QAM 256 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 48 -ANNEX A -QAM 256 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 96 -ANNEX A -QAM 256 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 6 -ANNEX A -QAM 16 -DDR -PRBS -MAX_TS 11 -Z 450 -M 869 –N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 12 -ANNEX A -QAM 16 -DDR -PRBS -MAX_TS 12 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 24 -ANNEX A -QAM 16 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 48 -ANNEX A -QAM 16 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 96 -ANNEX A -QAM 16 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 6 -ANNEX A -QAM 32 -DDR -PRBS -MAX_TS 11 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 12 -ANNEX A -QAM 32 -DDR -PRBS -MAX_TS 12 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 24 -ANNEX A -QAM 32 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 48 -ANNEX A -QAM 32 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 96 -ANNEX A -QAM 32 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 6 -ANNEX A -QAM 64 -DDR -PRBS -MAX_TS 11 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 12 -ANNEX A -QAM 64 -DDR -PRBS -MAX_TS 12 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 24 -ANNEX A -QAM 64 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 48 -ANNEX A -QAM 64 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 96 -ANNEX A -QAM 64 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 6 -ANNEX A -QAM 128 -DDR -PRBS -MAX_TS 11 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 12 -ANNEX A -QAM 128 -DDR -PRBS -MAX_TS 12 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 24 -ANNEX A -QAM 128 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 48 -ANNEX A -QAM 128 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6
gen_inp_cfg.pl -NOC 96 -ANNEX A -QAM 128 -DDR -PRBS -MAX_TS 24 -Z 450 -M 869 -N 1280 –BCF 600e6

Annex C

The following examples are for Annex C, 256-QAM and 64-QAM mapped channels with fDAC = 4608MHz, fOUT = 400MHz, and DDR. These mapped channels use internal PRBS data and have channel counts ranging from 1 to 128.
gen_inp_cfg.pl -NOC 1 -ANNEX C -QAM 256 -DDR -PRBS -MAX_TS 5 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 2 -ANNEX C -QAM 256 -DDR -PRBS -MAX_TS 5 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 4 -ANNEX C -QAM 256 -DDR -PRBS -MAX_TS 7 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 8 -ANNEX C -QAM 256 -DDR -PRBS -MAX_TS 11 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 16 -ANNEX C -QAM 256 -DDR -PRBS -MAX_TS 16 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 32 -ANNEX C -QAM 256 -DDR -PRBS -MAX_TS 32 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 64 -ANNEX C -QAM 256 -DDR -PRBS -MAX_TS 32 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 128 -ANNEX C -QAM 256 -DDR -PRBS -MAX_TS 32 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 8 -ANNEX C -QAM 64 -DDR -PRBS -MAX_TS 11 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 16 -ANNEX C -QAM 64 -DDR -PRBS -MAX_TS 16 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 32 -ANNEX C -QAM 64 -DDR -PRBS -MAX_TS 32 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 64 -ANNEX C -QAM 64 -DDR -PRBS -MAX_TS 32 -Z 450 -M 1889 -N 3643 –BCF 400e6
gen_inp_cfg.pl -NOC 128 -ANNEX C -QAM 64 -DDR -PRBS -MAX_TS 32 -Z 450 -M 1889 -N 3643 –BCF 400e6