Understanding the DS1WM Synthesizable 1-Wire Bus Master
Communication with 1-Wire® slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). This document describes the DS1WM, a synthesizable 1-Wire master that can be implemented in an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). The free DS1WM IP is available by request at https://support.maximintegrated.com/1-Wire.
With the growing popularity and diversity of 1-Wire devices, more engineers are facing the task of how to integrate a 1-Wire master into their systems. Reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications," describes various options. This document focuses on the DS1WM synthesizable 1-Wire bus master that can be implemented as a function block of an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). The DS1WM core uses little chip area (~3470 gates plus two bond pads). It also generates the entire 1-Wire timing by hardware, reducing the initial software development time and cost. Thus the entire application software can be written in high-level language. Besides the 1-Wire communication signal DQ, the DS1WM also provides a control signal STPZ, which assists in meeting the power requirements of certain 1-Wire slaves and allows for large networks with many slaves or extensive cabling. Figure 1 shows the typical DS1WM application circuit. The DS1WM is available for free in both Verilog and VHDL formats.
Similar to a memory device, the DS1WM connects to the user's system through an 8-bit data bus, using 3 address lines and the usual control signals (Figure 2). An internal divider chain converts any suitable system clock to a 1MHz signal, which in turn controls the 1-Wire timing. The DS1WM supports standard and overdrive 1-Wire communication in single-bit or byte mode, as well as modified timing for long line applications. The host interface and 1-Wire port signals are described in Table 1. Figures 3 to 5 and Table 2 specify the host interface waveforms and timing.
Figure 2. The DS1WM block diagram.
Table 1. Signal Descriptions
|MR||I||Master reset. Causes the DS1WM to perform an internal reset with the same result as a power-on reset. MR is not gated by
|CLK||I||System clock signal. The clock-divider block converts this signal into a ~1.0MHz clock, which in turn controls the 1-Wire timing. The duty cycle should be approximately 50%. See the Clock Divisor Register description for the logically permissible CLK frequencies. The physically permissible upper limit depends on the characteristics of the ASIC/FPGA chosen for implementation.|
|A[2:0]||I||Address lines of the host interface to access the various memory-mapped device registers. See the Memory Map for register addresses.|
||I||Active-low address strobe of the host interface. The state of the address lines A[2:0] is copied to an internal latch on the rising edge of the address strobe. See the Host Interface Timing diagrams (Figures 3, 4, and 5) for details.|
||I||Active-low general enable signal of the host interface. See the Host Interface Timing diagrams (Figures 3, 4, and 5) for details.|
|D[7:0]||I/O||Bidirectional data bus of the host interface, three-stated. The DS1WM drives these signals during the host read cycle (Figure 3). At all other times, these signals are in a high impedance state, allowing the host to communicate with other devices on the data bus.|
||I||Active-low write enable signal of the host interface. The state of the data bus D[7:0] is copied to the addressed register on the rising edge of the
||I||Active-low read enable signal of the host interface. When active, the DS1WM puts the contents of the selected register on the data bus for the host to read.
|DQ||I/O||IO driver for the 1-Wire bus. This is an open-drain bidirectional port, which requires a pullup resistor to VCC. For the permissible pullup resistor range, refer to the data sheet of the 1-Wire slaves in the application. The minimum value also depends on the drive characteristics and logic thresholds of the ASIC/FPGA chosen for implementation.|
|STPZ||O||Active-low control signal for an external P-channel transistor to bypass the pullup resistor at certain times. See the Control Register description, bits STPEN and STP_SPLY, and the STPZ timing diagrams (Figures 10 to 13) for details.|
|INTR||O||Interrupt signal of the host interface. The power-on default polarity is active low, but can be changed to active high through the IAS bit in the Interrupt Enable Register. The INTR signal is inactive unless interrupts are enabled through the Interrupt Enable Register and a qualifying interrupt condition exists. For details see the Interrupt Register description. Reading the Interrupt Register changes the INTR signal to its inactive state.|
Figure 3. Host interface write cycle.
Figure 4. Host interface read cycle.
Figure 5. Host interface timing, issuing a 1-Wire Reset.
Table 2. Host Interface Timing Specifications
|tADS||Address strobe width||Notes 1, 2||60||ns|
|tAH||Address hold time||Notes 1, 2||0||ns|
|tAR||Address latch to read||Notes 1, 2||60||ns|
|tAS||Address setup time||Notes 1, 2||60||ns|
|tAW||Address latch to write||Notes 1, 2||60||ns|
|tDH||Data hold time||Note 1||30||ns|
|tDS||Data setup time||Note 1||30||ns|
|tES||Enable setup time||Note 1||60||ns|
|tHZ||RD to floating data delay||Note 1||0||100||ns|
|tPDI||Presence detect to INTR||Note 1||0||100||ns|
|tRD||RD strobe width||Note 1||125||ns|
|tREN||Enable hold time from RD||Note 1||20||ns|
|tRVD||Delay from RD to data||Note 1||60||ns|
|tWEN||Enable hold time from WR||Note 1||20||ns|
|tWR||WR strobe width||Note 1||100||ns|
|tWRST||WR high to reset||Note 1||0||100||ns|
Note 1: These values depend on the process used to realize the DS1WM. Values shown are for example purposes only.
Note 2: If
%-overbar_pre%ADS%-overbar_post% is tied low, tAR and tAW are measured from tES. In this case, the falling edge of
%-overbar_pre%WR%-overbar_post% must occur at least tES + tAR or tES + tAW after the falling edge of
The host processor communicates with the DS1WM through 6 registers, which are accessed through 3 address lines A[2:0]. Table 3 shows the memory map.
Table 3. Memory Map
|03h||0||1||1||Write/read||Interrupt Enable Register|
|04h||1||0||0||Write/read||Clock Divisor Register|
This register is accessed to generate a 1-Wire reset/presence-detect cycle and to activate or deactivate the Search ROM accelerator. In addition to these two functions, the Command Register contains 2 bits to control the DQ pin directly.
Command Register Bitmap
|OW_IN: DQ Input (Read only)||
|FOW: Force 1-Wire||
|SRA: Search ROM Accelerator||
|1WR: 1-Wire Reset||
This is the location to which the host processor writes a data byte to be transmitted on the 1-Wire bus. If the 1-Wire slave is in a state to respond with data, the host writes a byte FFh to this register and then, after the byte is transmitted, reads this register again to retrieve that data sent by the 1-Wire slave.
|Data[7:0]: Transmit/Receive Data||
This register provides access to flags from current status, transmit, receive, and 1-Wire reset operations. All of these flags can generate an interrupt on the INTR pin if the corresponding enable bit is set in the Interrupt Enable Register. To clear the INTR signal, the Interrupt Register must be read. Reading the Interrupt Register always sets the INTR pin inactive even if not all flags are cleared.
Interrupt Register Bitmap
|OW_LOW: 1-Wire Event||
|OW_SHORT: 1-Wire Shorted||
|RSRF: Receive Shift Register Full||
|RBF: Receive Buffer Full||
|TEMT: Transmit Shift Register Empty||
|TBE: Transmit Buffer Empty||
|PDR: Presence Detect Result||
|PD: Presence Detect||
Interrupt Enable Register
The Interrupt Enable Register allows the system programmer to specify the source of interrupts which will cause the INTR pin to be active, and to define the active state for the INTR pin. When a Master Reset is received all bits in this register are cleared to 0 disabling all interrupt sources and setting the active state of the INTR pin to LOW. The INTR pin is reset to an inactive state by reading the Interrupt Register.
Interrupt Enable Register Bitmap
|EOWL: Enable 1-Wire Low Interrupt||
|EOWSH: Enable 1-Wire Short Interrupt||
|ERSF: Enable Receive Shift Register Full Interrupt||
|ERBF: Enable Receive Buffer Full Interrupt||
|ETMT: Enable Transmit Shift Register Empty Interrupt||
|ETBE: Enable Transmit Buffer Empty Interrupt||
|IAS: INTR Active State||
|EPD: Enable Presence Detect Interrupt||
Clock Divisor Register
The 1-Wire timing requires a 1MHz internal clock. The DS1WM generates this clock frequency from an external reference on the CLK pin. The external clock should have a 50% duty cycle is preferred. The Clock Divisor Register lets the host processor control a clock divider and prescaler to get from the external CLK signal as close as possible to the 1MHz needed for 1-Wire timing. The clock divisor must be configured before communication on the 1-Wire bus can take place. If using an FPGA, it is recommended to replace the clock-divider block with FPGA clock resources to generate the 1MHz internal clock. This avoids gated clocks in the FPGA.
Clock Divisor Register Bitmap
|CLK_EN: Enable 1-Wire Timing System||
|DIV[2:0]: Binary Divider Ratio||
|PRE[1:0]: Prescaler Ratio||
Table 4. Clock Divisor Register Settings
|Min CLK Frequency (MHz)||Max CLK Frequency (MHz)||Max CLK Error (%)||Overall Divider Ratio||DIV2||DIV1||DIV0||PRE1||PRE0|
Example: If the system clock frequency is 15MHz, the closest overall divider ratio to reach 1MHz is 14. This corresponds to a value of 87h to be written to the Clock Divisor Register. The clock error in this case is (15/14) -1, or 7%.
The host processor accesses this register to select the desired operating mode of the DS1WM. These modes include 1-Wire power delivery, recharge accelerator, single bit mode vs. byte mode, long line mode, and presence pulse masking. Correct use of these functions increases the data integrity on the 1-Wire bus.
Control Register Bitmap
1-Wire Port Description
The 1-Wire port uses the signals DQ and STPZ. The 1-Wire communication takes place on DQ. The DS1WM supports the following 1-Wire communication waveforms: reset/presence-detect cycle, write-zero time slot, write-one time slot, and read-data time slot.
This signal (Figure 6) consists of two elements: the DS1WM pulldown during the reset-low time tRSTL, and the tRSTH window during which, after a delay of tPDH, a 1-Wire slave pulls the line low for tPDL to signal its presence. To test for a presence pulse, the DS1WM first waits for tPDW and then during tPDSW samples the voltage on DQ. Note that the DS1WM does not control the duration of tPDH and tPDL.
The DS1WM can be configured to mask the presence generated by slaves (see Control Register, bit PPM). If the PPM bit is 1, the DS1WM generates a presence pulse (dotted line) that begins as tPPMS and lasts until tPPME.
Figure 6. Reset/presence detect cycle.
Write-Zero Time Slot
This time slot (Figure 7) consists of two elements: the DS1WM pulldown as specified by tW0L and the recovery time tREC0. The sum of tW0L and tREC0 is identical to tSLOT.
Figure 7. Write-zero time slot.
Write-One Time Slot
This time slot (Figure 8) consists of two elements: the DS1WM pulldown as specified by tW1L and the remainder of the time slot.
Figure 8. Write-one time slot.
Read-Data Time Slot
This time slot (Figure 9) consists of three elements: the DS1WM pulldown as specified by tW1L; the slave pulldown time; and the remainder of the time slot. At tMSR, the DS1WM samples the voltage on DQ. Note that a 1-Wire slave, when responding with a zero, starts pulling the DQ line low before tW1L is expired.
Figure 9. Read-data time slot.
Table 5. DQ Signal Timing Specifications (Note 1)
|τ||Time base period||(Note 2)||0.8||1||µs|
|tSLOT||Time-slot duration||Standard speed, LLM = 0||56||70||µs|
|Standard speed, LLM = 1||64||80|
|tW0L||Write-zero low time||Standard speed||48||60||µs|
|tW1L||Write-one/read low time||Standard speed, LLM = 0||4.8||6||µs|
|Standard speed, LLM = 1||6.4||8|
|tMSR||Read sample time||Standard speed, LLM = 0||12||15||µs|
|Standard speed, LLM = 1||19.2||24|
|tREC0||Write-zero recovery time||Standard speed, LLM = 0||8||10||µs|
|Standard speed, LLM = 1||16||20|
|tRSTL||Reset low time||Standard speed||480||600||µs|
|tRSTH||Reset high time||Standard speed||384||480||µs|
|tPDW||Presence-detect wait time||Standard speed, LLM = 0||8||10||µs|
|Standard speed, LLM = 1||8||10|
|tPDSW||Presence-detect sample window||Standard speed, LLM = 0||48.8||61||µs|
|Standard speed, LLM = 1||60.8||76|
|tPPMS||Presence-pulse mask START||Standard speed only||16||20||µs|
|tPPME||Presence-pulse mask end||Standard speed only||72||90||µs|
Note 1: The timing values depend on the internal logic. If the I/O drivers are slow, these times will change accordingly.
Note 2: System Clock CLK input frequency and Clock Divisor Settings according to Table 4.
If enabled (see Control Register, STPEN bit), the STPZ signal activates an external p-channel transistor at certain times to speed up the recharge of the 1-Wire bus. This function is generally needed at overdrive speed and with larger networks at standard speed. Figures 10 and 11 show the STPZ signal for the reset/presence-detect cycle and communication waveforms.
Figure 10. STPZ timing during the reset/presence detect cycle.
Figure 11. STPZ timing during read/write time slots.
Several 1-Wire slaves need extra power at certain times during the communication protocol. The extra power-supply delivery function is enabled through the STP_SPLY bit in the Control Register. If both STPEN and STP_SPLY are enabled, the STPZ signal remains active (low) whenever possible (see Figures 12 and 13).
Figure 12. STPZ timing with power delivery during the reset/presence detect cycle.
Figure 13. STPZ timing with power delivery during read/write time slots.
Table 6. STPZ Timing Specifications (Note 1)
|tON1||Active time for presence detect||Standard speed||6.4||8||µs|
|tON2||Active time for presence detect recovery||8||10||µs|
|tON3||Active time for write-one recovery (Notes 2, 3)||Standard speed||51.2||64||µs|
|tON4||Active time for write-zero recovery (Notes 2, 3)||Standard speed||6.4||8||µs|
|tDLY1||Delay time for presence detect||0.8||1||µs|
|tDLY2||Delay time for presence detect recovery (Note 4)||Standard speed||399.2||499||µs|
|tDLY3||Delay time for write-one and write-zero recovery||0.8||1||µs|
|tOFF1||Turn-off time for 1-Wire Reset||1.6||2||µs|
|tOFF2||Turn-off time for write-one and write-zero||(Note 5)||0.8||1||µs|
Note 1: The timing values depend on the internal logic. If the I/O drivers are slow, these times will change accordingly.
Note 2: There is no timing difference for sending out and receiving bits within a byte. The difference comes when the last bit of the byte is finished being sent out. At this point, the signal is either enabled continuously until the next reset or time slot begins, or enabled only for tON3 or tON4.
Note 3: When performing a read versus a write time slot, the master provides the same active time for write-one and write-zero. However, the input from the DQ line is sensed every 1µs for a high value. If DQ is high, the STPZ signal is enabled. If the DQ line is low, the STPZ signal remains disabled until the high is sensed. In all write time slots, a high is sensed immediately.
Note 4: This parameter is the time delay until the master begins to monitor the DQ input level. If the line is already high, then STPZ will be enabled. If not, it will wait to enable STPZ until the next state machine clock after the DQ line has recovered.
Note 5: The very first bit in a byte transmission has an extended tOFF2 of 4µs due to the order of states the master's state machine runs through.
After power-on, the host first accesses the Clock Divisor Register to write the appropriate values for the prescaler and divider and to enable the 1-Wire timing system. If the application uses the STPZ output, the STPEN bit in the Control Register must be set. If the application uses the INTR signal, the host writes to the Interrupt Enable Register to define the INTR active state polarity and to select the conditions under which the INTR signal is to be activated. This concludes the setup phase. Now the DS1WM is ready to operate at standard speed and in byte mode.
Generating a 1-Wire Reset/Presence-Detect Cycle
The host writes the code 01h to the Command Register. If the Presence Detect Interrupt is enabled (EPD bit), the host could perform other tasks while the DS1WM is busy with the reset/presence-detect cycle. After the cycle is completed, the host reads the Interrupt Register (PDR bit) to see whether a presence pulse was detected.
Writing a Byte to the 1-Wire Line
To send a byte on the 1-Wire bus, the user writes the desired data to the Transmit Buffer. The data is then moved to the Transmit Shift Register where it is shifted serially onto the bus LSB first. A new byte of data can then be written to the Transmit Buffer. As soon as the Transmit Shift Register is empty, the data will be transferred from the Transmit Buffer and the process repeats. Each of these registers has a flag that may be used as an interrupt source. The Transmit Buffer Empty (TBE) flag is set when the Transmit Buffer is empty and ready to accept a new byte. As soon as a byte is written into the Transmit Buffer, TBE is cleared. The Transmit Shift Register Empty (TEMT) flag is set when the Shift Register has no data in it and is ready to accept a new byte. As soon as a byte of data is transferred from the Transmit Buffer, TEMT is cleared and TBE is set.
Reading a Byte from the 1-Wire Line
To read data from the 1-Wire bus, a slave device must first be ready to transmit depending on commands already received from the DS1WM. Reading from the 1-Wire line is similar to writing. The host initiates a read by writing an FFh byte to the Transmit Buffer. The wired-AND of the written data and the data from the slave device is then shifted into the Receive Shift Register. When the Receive Shift Register is full, the data is transferred to the Receive Buffer, where it can be accessed by the host. If the slave device is not ready to transmit, the data received is identical to that transmitted. The Receive Buffer Register can also generate interrupts. The Receive Buffer flag (RBF) is set when data is transferred from the Receive Shift Register and cleared when the host reads the register. If RBF is set, no further transmissions should be made on the 1-Wire bus or else data may be lost, as the byte in the Receive Buffer will be overwritten by the next received byte.
1-Wire Communication in Bit Mode
To activate the bit mode, the host writes the BIT_CTL bit in the Control Register to 1. Subsequent communication between host and DS1WM is the same as in byte mode. However, only the least significant bit in the transmit/receive buffer is relevant.
Changing Between Standard and Overdrive Speed
To switch between 1-Wire speeds, the host writes the OD bit in the Control Register to 1 (overdrive) or to 0 (standard). Any 1-Wire communication after updating the OD bit takes place at the new speed. Long line mode (LLM bit) is a variant of standard speed.
Meeting Slave Extra Power Requirements
The 1-Wire slave data sheets specify when, during a function command, extra power is required. To accommodate such a slave, the host operates the DS1WM using reset, byte, or bit functions to get the slave close to the state where the extra power is needed. Then the host sets both the STPEN and the STP_SPLY bits in the Control Register. Next the host performs the byte or bit read/write operation, after which the slave needs extra power. Then the host waits until the high-power phase is over and accesses the Control Register again to write the STP_SPLY bit to 0. The STPEN bit can remain set. The power delivery function works only if the STPZ pin is connected to a transistor, as shown in Figure 1.
Application note 187, "1-Wire Search Algorithm," explains how the Search ROM function works. The search accelerator is a feature that minimizes the communication between host and DS1WM when performing a 1-Wire search. The search accelerator of the DS1WM is identical to the accelerator in the DS2480B. Therefore, the search fundamentals of application note 192, "Using the DS2480B Serial 1-Wire Line Driver" ("OWSearch" section), are also valid for the DS1WM. Of course, the DS2480B-specific command and echo bytes do not apply here.
Before the search accelerator can be used, a 1-Wire reset/presence-detect cycle must have been performed and the Search ROM command (F0h) must have been sent out in byte mode. Now the search accelerator is activated by writing the SRA bit in the Command Register to 1.
After the search accelerator is activated, the host must send 16 bytes to complete a single Search ROM pass on the 1-Wire bus. These bytes are constructed as follows:
In this scheme, the index (values from 0 to 63, "n") designates the position of the bit in the ROM ID of a 1-Wire device. The character "x" marks bits that act as a filler and do not require a specific value (don't care bits). The character "r" specifies the selected bit value to write at that particular bit in case of a conflict during the execution of the ROM search.
For each bit position n (values from 0 to 63) the DS1WM generates three time slots on the 1-Wire bus. These are referenced as:
|b0||for the first time slot (read data)|
|b1||for the second time slot (read data)|
|b2||for the third time slot (write data)|
The DS1WM determines the type of time slot b2 (write-one or write-zero) as follows:
|b2||= rn if conflict (as chosen by the host)|
|= b0 if no conflict (there is no alternative)|
|= 1 if error (there is no response)|
The 16 response bytes that the host reads from the Receive Buffer during a complete pass through a Search ROM function using the search accelerator are constructed as follows:
As before, the index (values from 0 to 63, "n") designates the position of the bit in the ROM ID of a 1-Wire device. The character "d" marks the discrepancy flag in that particular bit position. The discrepancy flag is 1 if there is a conflict or no response in that particular bit position, and 0 otherwise. The character " r' " marks the actually chosen path at that particular bit position. The chosen path is identical to b2 for the particular bit position of the ROM ID.
To perform a Search ROM sequence, one starts with all bits rn being 0s. In case of a bus error, all subsequent response bits r'n are 1's until the Search Accelerator is deactivated by writing the SRA bit in the Command Register to 0. Thus, if r'63 and d63 are both 1, an error has occurred during the search procedure and the last sequence must be repeated. Otherwise r'n (n = 0...63) is the ROM ID of the device that has been found and addressed. If the host wishes to execute a memory function with this slave, first the search accelerator needs to be deactivated.
If the host wants to continue with the ROM search to identify the remaining 1-Wire slaves, it first must instruct the DS1WM to turn off the search accelerator, perform a 1-Wire reset/presence-detect cycle, and transmit the Search ROM command. Then the search accelerator must be activated again.
For the next Search ROM sequence, reuse the previous set rn (n = 0…63) but set rm to 1, with "m" being the index number of the highest discrepancy flag that is 1, and set all ri to 0 with i > m.
All parts are found if the highest discrepancy occurs in the same bit position for two consecutive passes.
FPGAs or ASICs integrate the designed DS1WM. In Figure 14, the design module with a microprocessor can offload the 1-Wire communication to the DS1WM.
Figure 14. Typical FPGA or ASIC application.
The industry typically denotes the level of verification of an IP block with the following conventions:
- Gold IP has been to target silicon.
- Silver IP has been to target silicon in FPGA.
- Bronze IP has been verified in silicon models with logical timing closure.
- In-development IP has not yet been verified.
Note: The DS1WM has achieved silver status.
The DS1WM package comes complete with:
- Verilog HDL
- Verilog test bench
- Readme information on setup and scripts
The free DS1WM IP is available by request at https://support.maximintegrated.com/1-Wire.
The DS1WM synthesizable 1-Wire bus master is an alternative to performing 1-Wire communication through "bit-banging." It can be embedded in an FPGA or ASIC, where it appears as a memory-mapped device. The DS1WM supports the communication- and power-delivery requirements of all 1-Wire slave devices.