应用笔记 5477

Analyzing Audio DAC Jitter Sensitivity

By: Matt Felder

摘要 : This application note describes how sampling clock jitter (time interval error or \"TIE jitter\") affects the performance of delta-sigma digital-to-analog converters (DACs). New insights explain the importance of separately specifying low-frequency (< 2x passband frequency) and high-frequency or wideband (> 2x passband frequency) jitter tolerance in these devices. The article also provides an application example of a simple highly jittered cycle-skipped sampling clock and describes a method for generating a proper broadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance to competitor audio DACs. Maxim's exceptionally high jitter tolerance allows very simple and low-cost sample clock implementations.