关键词: DDR1, DDR3, jitter, buffer, TDMoP, TDM over packet, DDR, SDRAM, PDV, PSN, double data rate
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'elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin eter TCK_MIN 1875; // tCK ps Minimum Clock Cycle Time eter TJIT_PER 90; // tJIT(per) ps Period JItter eter TJIT_CC 180; // tJIT(cc) ps Cycle to Cycle jitter eter TERR_2PER 132; // tERR(2per) ps Accumulated Error (2-cycle) eter TERR_3PER 157; // tERR(3per) ps Accumulated Error (3-cycle) eter TERR_4PER 175; // tERR(4per) ps Accumulated Error (4-cycle) eter TERR_5PER 188; // tERR(5per) ps Accumulated Error (5-cycle) eter TERR_6PER 200; // tERR(6per) ps Accumulated Error (6-cycle) eter TERR_7PER 209; // tERR(7per) ps Accumulated Error (7-cycle) eter TERR_8PER 217; // tERR(8per) ps Accumulated Error (8-cycle) eter TERR_9PER 224; // tERR(9per) ps Accumulated Error (9-cycle) eter TERR_10PER 231; // tERR(10per)ps Accumulated Error (10-cycle) eter TERR_11PER 237; // tERR(11per)ps Accumulated Error (11-cycle) eter TERR_12PER 242; // tERR(12per)ps Accumulated Error (12-cycle) eter TDS 75; // tDS ps DQ and DM input setup time relative to DQS eter TDH 100; // tDH ps DQ and DM input hold time relative to DQS eter TDQSQ 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access eter TDQSS 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition eter TDSS 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) eter TDSH 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) eter TDQSCK 300; // tDQSCK ps DQS output access time from CK/CK# eter TQSH 0.38; // tQSH tCK DQS Output High Pulse Width eter TQSL 0.38; // tQSL tCK DQS Output Low Pulse Width eter TDIPW 490; // tDIPW ps DQ and DM input Pulse Width eter TIPW 780; // tIPW ps Control and Address input Pulse Width eter TIS 275; // tIS ps Input Setup Time eter TIH 200; // tIH ps Input Hold Time eter TRAS_MIN 37500; // tRAS ps Minimum Active to Precharge command time eter TRC 52500; // tRC ps Active to Active/Auto Refresh command time eter TRCD 15000; // tRCD ps Active to Read/Write command time eter TRP 15000; // tRP ps Precharge command period eter TXP 7500; // tXP ps Exit power down to a valid command eter TCKE 5625; // tCKE ps CKE minimum high or low pulse width eter TAON 300; // tAON ps RTT turn-on from ODTLon reference eter TWLS 245; // tWLS ps Setup time for tDQS flop eter TWLH 245; // tWLH ps Hold time of tDQS flop eter TWLO 9000; // tWLO ps Write levelization output delay eter TAA_MIN 15000; // TAA ps Internal READ command to first data eter CL_TIME 15000; // CL ps Minimum CAS Latency