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Implementing Host Based HDLC Using Quasi-Synchronous Mode

关键词: V.42, MNP 2-4 error correction, SDLC, HDLC, quasi-synchronous, asynchronous to synchronous conversion, Teridian, V.22bis, synchronous data link control, DTE, high-level data link control
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应用笔记 5006

Implementing Host Based HDLC Using Quasi-Synchronous Mode

By: Jeff Sorensen

摘要 : The Teridian 73M2901CE single-chip, V.22bis modem supports a host-based software module for V.42/MNP 2-4 error-correction protocols, synchronous data link control (SDLC), and high-level data link control (HDLC) operation. These operations require the 73M2901CE's special quasi-synchronous mode, which performs an asynchronous-to-synchronous conversion (and vice versa) to data going over the data-terminal-equipment (DTE) interface. This application note describes how to implement host-based HDLC and SDLC operations using the 73M2901CE's quasi-synchronous mode.