应用笔记 4565

Ramp Generator Controls DC-DC Converters

By: Eric Schlaepfer

摘要 : This circuit, based on a MAX6877, generates a sequence of three fixed-slew-rate ramps for driving as many DC-DC converters as necessary. Two or more supply voltages can be made to track by connecting their TRACK pins to the same ramp output, or the voltages can be sequenced by connecting their TRACK pins to separate ramp outputs.

A similar version of this article appeared in the January 21, 2007 issue of EE Times magazine.

The output of many DC-DC converters can be made to track an applied ramp or other voltage waveform, and the application notes for modern point-of-load power supplies often describe circuits that track or sequence multiple voltages. The inexpensive approach of Figure 1, for example, applies the exponential curve of a series-RC network as the reference ramp. Its simplicity brings several drawbacks, however. The ramp slope varies with time, and the output voltages can only be tracked as a group.

Figure 1. Simple ramp-tracking circuit.
Figure 1. Simple ramp-tracking circuit.

The Figure 2 circuit generates a sequence of three fixed-slew-rate ramps, which can drive as many DC-DC converters as necessary. Two or more supply voltages can be made to track by connecting their TRACK pins to the same ramp output, or the voltages can be sequenced by connecting their TRACK pins to separate ramp outputs. The FETs shown can be any small-signal FET, such as the 2N7002. Timing and slew rates are controlled by small capacitors.

Figure 2. This specialized IC (MAX6877) generates three independent ramps for use in supply-voltage tracking and sequencing.
Figure 2. This specialized IC (MAX6877) generates three independent ramps for use in supply-voltage tracking and sequencing.

This circuit also monitors the 5V intermediate bus, and begins the power-up sequence only when the 5V bus voltage exceeds a threshold set by the resistive divider. When power-up is complete, the System Reset output goes high. An oscilloscope plot (Figure 3) shows the timing relationships of the three ramps and the System Reset signal.

Figure 3. These timing waveforms illustrate operation of the Figure 2 circuit.
Figure 3. These timing waveforms illustrate operation of the Figure 2 circuit.