应用笔记 4509

DC Voltage Controls PWM Dimming of High-Brightness LEDs (HB LEDs)

By: Jim Christensen

摘要 : This LED-driver circuit includes a hysteretic controller U1 (MAX16820), related power components, and a control circuit based on the quad op amp U2 (LMX324). U1 drives five HB LEDs from a 24V source, using only inductor L1, MOSFET Q1, and catch diode D1.

A similar version of this article appeared in the June 24, 2008 issue of Electronic Design magazine.

High-brightness LEDs (HB LEDs) are making inroads into the more traditional lighting that includes a DC distribution system (an example is the 24V MR-16 track lights). HB LEDs are more efficient, and they have a potentially longer lifespan than do halogen or xenon lamps.

Because hysteretic controllers are inexpensive, bring simplicity to lighting designs, and require no compensation networks, they are well suited for driving HB LEDs. Hysteretic controllers usually have a Pulse Width Modulator (PWM) input that enables a pulse train of varying duty cycle to provide the dimming function. One problem, however, in converting a traditional lighting system is that many dimmers provide a 1V-10V DC signal rather than a PWM signal. To increase the HB LED operating lifetimes, a controller should also provide temperature-based current foldback.

Converting a DC voltage to a PWM signal is easy. The PWM signal appears at the output of a comparator when you apply the DC voltage at one input and a triangle wave at the other. Headaches can arise, however, in trying to align the triangle wave with the control voltage. You want a linear relationship between duty cycle and control voltage, with a 0% duty cycle at the minimum control voltage and a 100% duty cycle at the maximum.

The schematic of Figure 1 includes the hysteretic controller U1 (MAX16820), related power components, and a control circuit based on the quad op amp U2 (LMX324). U1 drives five HB LEDs from a 24V source, using only inductor L1, MOSFET Q1, and catch diode D1. A sense resistor (R1) sets the current to 0.5A. U1 turns on Q1 whenever the current-sense voltage drops below 190mV, and turns Q1 off when that voltage exceeds 210mV. Hysteretic controllers have no clock and require no external compensation. Figure 2 illustrates the current-sense waveform corresponding to a small ON-time in the PWM signal. U1 also provides a regulated 5V for supplying power to the PWM conversion circuitry.

Figure 1. While driving five HB LEDs, this circuit provides DC-controlled dimming and temperature-based current foldback.
Figure 1. While driving five HB LEDs, this circuit provides DC-controlled dimming and temperature-based current foldback.

Figure 2. This current-sense waveform from the Figure 1 circuit shows the HB LED current at a low duty cycle.
Figure 2. This current-sense waveform from the Figure 1 circuit shows the HB LED current at a low duty cycle.

The difficulty in converting a control voltage to a PWM signal is in setting the triangle wave's peak and valley voltages to closely match the corresponding maximum and minimum values of the control voltage (VCNTL). Two op amps in U2 generate the triangle wave, which oscillates between an upper voltage level set by the R7–R8 divider, and a lower voltage level set by the R7–R8||R9 divider. The output of U2A is a 50% duty cycle, rail-to-rail square wave. Setting U2B+ equal to VCC/2 causes the U2B output to integrate the square wave, producing a symmetrical and linear triangle wave. R10 and C4 set the operating frequency.

Achieving 0V at the valley of the triangle wave is difficult, because the U2B output has a worst-case minimum of 60mV. We therefore choose a valley of 250mV and a peak of 2V. Because VCNTL ranges from 0V to 10V, R12–R13 divides VCNTL by 5, limiting the reduced control voltage, VRED, to 2.0V and thereby matching the triangle wave's peak voltage. U2D creates the PWM pulse train by comparing the triangle wave to VRED. The triangle-wave valley is 250mV, so the PWM signal remains at 0% until VCNTL reaches 1.25V. This action causes a small offset error that is most pronounced at low values of VCNTL, but it also confers an advantage by guaranteeing an OFF position. Figure 3 shows how the triangle wave converts the divided control voltage into a pulse-width modulated waveform.

Figure 3. Also from Figure 1, these waveforms show a 16% duty cycle for VCNTL = 2V.
Figure 3. Also from Figure 1, these waveforms show a 16% duty cycle for VCNTL = 2V.

Op amp U2C provides the temperature-based current foldback. The R4/R5/R6 divider delivers 1.5V to the noninverting input of U2C, which is almost a diode drop below the triangle wave's peak (2V). Thermistor R2 (a resistor with negative temperature coefficient) is nominally 100kΩ at 25°C, but its value declines to 33kΩ at 50°C. At that temperature the R2–R3 divider produces 1.5V—a balance point at which U2C's positive, negative, and output terminals are all at 1.5V, and just about to pull VRED lower, via D2. At 70°C, R2 drops to 15.5kΩ and the op amp output drops to 1.0V, pulling VRED to about 1.6V. This action achieves the desired current foldback by limiting the maximum duty cycle at 70°C to 80%. A simple change of resistor values allows the circuit to accept different VCNTL ranges, and to have different temperature-foldback characteristics.
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APP 4509:
应用笔记 4509,AN4509, AN 4509, APP4509, Appnote4509, Appnote 4509