Low-Temperature Data Retention in Nonvolatile SRAM
Low-power SRAM has historically been the obvious solution for nonvolatile memory applications, primarily due to the very low supply currents required to reliably maintain system data during external power loss. This parameter is typically identified as data retention current (ICCDR).
Battery component selection in a design usually comes down to a trade-off between the desired system data-retention time and the physical size of the required lithium cell. This discussion does not address the physical cell size as a constraint in the design, so two similarly sized 20mm coin cells were evaluated.
In Figure 1 the ambient data-retention current consumption of three different memory components is illustrated. The memory densities differ quite significantly and the voltage dependency in those measured currents also varies among the samples. Nonetheless, all three memory components appear to meet the basic low-current requirements for extended data retention under battery-backup conditions.
Figure 1. SRAM data retention current.
The graph clearly shows that the Vendor X 256kb sample possesses both a higher quiescent current and a more pronounced voltage acceleration slope than the other SRAM samples analyzed.
Figure 2. BR2032 voltage vs. temperature.
In Figure 2, a BR2032 primary (nonrechargeable) lithium coin cell (190mAh nominal capacity) was subjected to various load conditions across the indicated temperature range. From the chart, the cell voltage under any of the listed loads was ~3.4V at +25°C.
Referencing the Vendor X 256kb current characteristic (Figure 1), we can then determine that this specific SRAM will require ~1.2µA of battery current with 3.4V applied. Given the BR2032 cell capacity rating, the expected ambient data-retention time would be in excess of 19 years. There is, however, a historic drawback with using most batteries: when depleted, they must be replaced.
Also observed in Figure 2 is a detectable change in the cell performance at reduced temperatures. As the various loads were applied, the departure in the measured voltages was initially observed at +25°C. The deviation is more pronounced as the load-current requirement increased. This loss of battery efficiency is due to the slowing of the electrochemical reaction as the temperature decreases.
To understand the battery behavior in Figure 2, we turn again to the Figure 1 "Vendor X 256kb" ICCDR characteristic. We can then estimate that this SRAM provides a 3MΩ equivalent load to the cell.
Figure 3. ML2020R voltage vs. temperature.
In the Figure 3 graph, a ML2020R secondary (rechargeable) lithium coin cell (30mAh nominal capacity) was subjected to various load conditions across the indicated temperature range. From the chart, the charged cell voltage under any of the listed loads is ~2.8V at +25°C.
Using the same Vendor X 256kb I/V characteristic, the reduction in nominal bias from the ML2020R cell gives the user an immediate 35% reduction in the required SRAM current. The estimated ambient data-retention time would then be ~5.4 years, or 28% of that using a BR2032, even though the stated capacity is only 15% of that hefty primary cell.
Factoring in that the ML2020R can be fully depleted and recharged up to 15 times, this translates to over 80 years of field life expectancy for the system using these specific components. This lifetime expectancy assumes that the system could be powered on for ~3 days at least once every 5 years.
For comparison and again using the Figure 1 Vendor X 256kb ICCDR characteristic, we can estimate that the SRAM provides a 4.5MΩ equivalent load to this cell, due solely to the reduction in the applied bias.
Further, as observed on the BR2032 cell (Figure 2), the ML2020R has a similar, but less pronounced change in cell performance at reduced temperatures. Under the same loads applied to the other battery, the departure in the ML2020R measured voltages was initially observed at -15°C. It is again more pronounced as the load-current requirement increased.
Figure 4. SRAM data retention current (ICCDR at -40°C).
The Figure 4 chart is the result of the same bias applied to the three samples illustrated in Figure 1, but now the component case temperature is -40°C.
Given the same Vendor X 256kb, the reduction in temperature raises the on-chip transistor thresholds enough to cut off any parasitic leakage paths within the memory chip. This effectively increases the SRAM load to be greater than 11MΩ if using a BR2032, or greater than 20MΩ if using a ML2020R.
ConclusionFor backup supply load calculations, the effective resistance of a low-power CMOS memory is inversely proportional to the temperature. This relationship is illustrated in Figure 5, using the typical bias applied by the battery samples analyzed.
Figure 5. SRAM effective loading.
When comparing the SRAM effective resistance (Figure 5) to the battery current-delivery capabilities (Figures 2 and 3), it becomes clear that the worst-case SRAM load resistance over this temperature range is well above the region of any electrochemical efficiency loss for either battery chemistry.
Either battery will perform effectively for, at a minimum, over 5 years of continuous battery backup using any of the sampled memory components.