In addition, laser drivers that have two closed-loop controls need a way of setting APC and modulation currents set points. Conventionally this has been done using mechanical potentiometers first, then these mechanical pots are replaced with fixed resistors selected to have equal values.
This process relies on having fixed-value resistors to be close to the measured value of the pots. In practice, the fixed resistors do not match the pot values and the end result is that the optical-output power differs from the required settings. Therefore, it is introducing an error that translates into a larger optical-output power variation in the power budget.
The EEPROM could be used for serial ID information required in some modules. The module footprint could be either SFF or SFP compliant.
Figure 1. Typical optical module block diagram.
Figure 2 shows connection details for using DS3902 and a serial EEPROM (ATmel AT24C02) on a common I2C interface. Also Figure 2 illustrates connections to a laser driver.
Figure 2. Schematic for LD, DS3902, and AT24C02.
The DS3902's default address is A2h (Add_sel = 0). If an address different from A2h is required, Add_sel will be pulled high. Register 00h content is the device address when Add_sel = 1. In the above schematic AT24C02 is configured for A0h address, (A0 = A1 = A2 = 0).
The WP (write-protect) pin connects to ground using a link, allowing R/W access to memory locations. Once the memory is programmed, the WP pin can be pulled high through LK1, to prevent accidental write. DS3902 has S/W protection scheme, whereby access to memory is only possible with password.
The choice of laser driver depends on the specific application and there are a number of Maxim laser drivers to choose from.
Laser drivers incorporate a number of features including:
Some laser drivers incorporate pulse-width control of the incoming signal stream as well as clock input for better jitter performance.
In addition loss-of-signal detection is done typically in the limiting amplifier stage, and flagged to the host board with a logic-high level. Threshold and sampling time adjustment may also be incorporated in this stage.
A typical slow-start circuit is depicted here. This is a low-cost design with minimum of component counts.
Figure 3. Schematic diagram for low-cost, slow-start, power supply design.
All components are SMD and available in small foot prints. M1 is a PMOS and should be selected for adequate current ratings and minimum voltage drops across it when supplying full current. Component values could be adjusted if needs be. The values given here provide a practical slow-start timing.
The following diagram for RL=9Ω is a 360mA load, and timing delay is given for three values of C3.
The above is response to a step-input voltage 0V to 3.3V. The current surge is well below the 360mA maximum current output with the component values given in the schematic.