应用笔记 1032

MAX3670: Loop-Filter Configuration for the MAX3670 Low-Jitter PLL Reference Clock Generator


摘要 : The MAX3670 low-jitter clock generator is a monolithic phase-locked loop (PLL) that uses an externalhigh-Q voltage-controlled oscillator (VCO) to create a very low jitter clock signal phase-locked to a systemclock input. It is ideal for SONET OC-48 or OC-192 applications requiring a very low jitter 156 MHZ or 622MHz clock signal. When used with a low-jitter voltage-controlled SAW oscillator (VCSO) or avoltage-controlled crystal oscillator (VCX), the total system jitter can be less than 1 psrms. This designnote provides analysis and examples that address optimal PLL configuration, including externalcomponent values, internal divider settings, and internal phase detector gain for low-jitter applications.


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APP 1032:
应用笔记 1032,AN1032, AN 1032, APP1032, Appnote1032, Appnote 1032