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MAXREFDES44#:采用1-WIRE ECDSA和XILINX ZYNQ SOC的安全认证设计

MAXREFDES44

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描述

MAXREFDES44#为基于1-Wire®的安全认证参考设计,用于保护IP以及外设与Xilinx Zynq™ FPGA之间的安全认证。利用提供的示例代码,系统与DS28E35执行不对称质询-应答序列,以确保模块、外设或子系统的真实性。DS28E35通过Maxim Integrated的1-Wire总线通信。MAXREFDES44#配备有Pmod™连接器,以便利用Avnet MicroZed™立即进行测试。设计的简单性确保快速适应要求不对称ECDSA算法提供增强安全性的任何外设。

更多信息请参考详细资料标签页。包括原理图、PCB文件及物料单(BOM)在内的设计文件可从设计资源标签页下载。根据申请,在签署保密协议之后可提供固件。

注:对MAXREFDES44#进行编程要求单独购买DS28E35EVKIT#。

特征

  • ECDSA安全认证
  • 1-Wire接口
  • 源代码示例
  • Pmod兼容规格

竞争优势

  • 强加密安全认证
  • 带硬件加速,实现快速性能
  • 外设安全认证不要求VCC引脚

应用

  • 网络附加设备的安全认证(IoT)
  • 严防假冒
  • 外设安全认证
  • IP保护
  • 许可证与功能管理

  • maxrefdes44fig00

    maxrefdes44fig00

  • maxrefdes44fig02

    maxrefdes44fig02

  • maxrefdes44fig01

    maxrefdes44fig01

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设计, 制作, 测试

图中的电路板已经完成封装和测试。

 

细节部分

细节部分

Introduction

Smart factories and applications for industrial and medical employ the flexibility and high performance of modern SoCs. As these systems become increasingly connected, security emerges as a paramount feature to protect IP, track product lifetime, and prevent counterfeiting. The MAXREFDES44# is a 1-Wire based asymmetric authentication reference design, built to authenticate peripherals to Xilinx SoCs. The public keys are stored on the Xilinx SoC, relieving the need for a secure secret memory location, while the private key is stored on the DS28E35 using DeepCover® technology. Using the provided example code, the SoC executes a challenge response sequence with the DS28E35 to ensure the authenticity of a module, peripheral, or subsystem. The DS28E35 communicates on a 1-Wire bus, providing a standard communication interface. The MAXREFDES44# hardware, shown in Figure 1, is equipped with a Pmod-compatible connector for immediate testing using an Avnet MicroZed evaluation kit. The simplicity of this design enables rapid adoption into any peripheral requiring the heightened security provided by the asymmetric ECDSA algorithm.

MAXREFDES44 DS28E35 peripheral module (top and bottom). Figure 1. MAXREFDES44 DS28E35 peripheral module (top and bottom).

Detailed Description of Hardware

The system shown in Figure 2 shows the high-level implementation of the design. The system requires:

  • Cheyenne ‘C’ code running on the ARM® Cortex® A9 processor in the Processing System (PS)
  • Cryptographically Secure Pseudo Random Number Generator (CSPRNG) running in the Programmable Logic (PL)
  • PC connected to a RS-232 port (USB UART)
  • MAXREFDES44# with the DS28E35 and a 680Ω pullup resistor

System design block diagram.Figure 2. System design block diagram.

Hardware
The hardware setup for this reference design is:

  • PC with 1GB RAM
    • www.xilinx.com/design-tools/vivado/memory.htm
  • Avnet MicroZed (available by Avnet for purchase separately)
  • Maxim DS28E35 peripheral module (MAXREFDES44# available for purchase)
    • Available for immediate download on the Design Resources tab is the schematic, BOM, and PCB Gerber
  • USB-A to USB-micro B cable
  • Xilinx platform cable USB
  • DS28E35EVKIT# (2nd generation with DS2475 available for purchase separately) used for programming only

Software
The software requirements for this reference design are:

Detailed Description of Firmware

The archived Vivado project, “MAXREFDES44.xpr.zip”, contains all the details of the PS and PL. The archive has a basic Zynq configuration that contains Avnet’s MicroZed Board Definition for 2014.2 and additional modifications to add a CSPRNG needed for security. Avnet’s MicroZed Board Definition for 2014.2 can be found on their MicroZed website under documentation. Figure 3 shows the block diagram for the design found under the “\MAXREFDES44.xpr\MZ_Zynq_HW” path and called “MZ_Zynq_HW.xpr”.

Block diagram of Zynq.Figure 3. Block diagram of Zynq.

The PS and PL configuration block diagram is shown in Figure 4.

PS-PL configuration block diagram.Figure 4. PS-PL configuration block diagram.

The essential MIO configurations used in this reference design are the UART and GPIO interfaces shown in Figure 5. UART 1 is used to communicate to a terminal program for external print statements to be outputted on MIO48(tx) and MIO49(rx). GPIO has connections to MIO15 (1-Wire) and the EMIO GPIO with a width of one used for an internal connection to the CSPRNG (rng_top_0). All the other MIO configurations are the default settings from the Avnet’s MicroZed Board Definition, which are not used for this reference design.

Block diagram of the Zynq MIO configuration.Figure 5. Block diagram of the Zynq MIO configuration.

The clock configuration is set to use Avnet’s MicroZed board definition defaults with the exception being that the FCLK_CLK0 signal is enabled and used to source the CSPRNG as shown in Figure 6.

Block diagram of the Zynq clock configuration.Figure 6. Block diagram of the Zynq clock configuration.

The CSPRNG is an exclusive-or of the outputs of two ring oscillators with two different periods and is sampled by the FCLK_CLK0 signal to make random numbers. Because of the two ring oscillators, this creates a combinatorial loop in the PL which usually creates an error when building the design. To overcome the error and make it a warning, the tcl file “project_setup.tcl” is to be run in the tcl console before running the full build. The file can be found under the “/MAXREFDES44/MZ_Zynq_HW” path.

Quick Start

Required Equipment:

  • Windows® PC with two USB ports
  • MAXREFDES44# board
  • MAXREFDES44# supported platform (i.e., the MicroZed kit)
  • Programming cable (i.e., the platform cable USB II or equivalent)
  • DS28E35EVKIT# (2nd generation with DS2475)

Download, read, and carefully follow each step in the appropriate MAXREFDES44# Quick Start Guide.


1-Wire and DeepCover are registered trademarks of Maxim Integrated Products, Inc.
ARM is a registered trademark and registered service mark of ARM Limited.
Cortex is a registered trademark of ARM Limited.
Eclipse is a trademark of Eclipse Foundation, Inc.
HyperTerminal is a registered trademark of Hilgraeve, Incorporated.
MicroZed is a trademark of Avnet, Inc.
Pmod is a trademark of Digilent Inc.
Vivado and Zynq are registered trademarks of Xilinx, Inc.
Windows is a registered trademark and registered service mark of Microsoft Corporation.
Xilinx is a registered trademark and registered service mark of Xilinx, Inc.

Maxim设备 (1)

器件号 名称 产品线 购买 设计套件和评估模块
DS28E35 DeepCover 1-Wire ECDSA认证器,带有1Kb用户EEPROM 安全认证器件 立即购买 Design Kits

Maxim设备 (1)

器件号 产品线
安全认证器件
DeepCover 1-Wire ECDSA认证器,带有1Kb用户EEPROM

参考指南

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