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MAXREFDES74#:18位高精度数据采集系统

MAXREFDES74#

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描述

概述

MAXREFDES74#参考设计执行高速、18位、高精度数据采集,基于Maxim的前沿、高精度、低功耗数据转换器。MAXREFDES74#设计作为一个模块,适用于工业过程控制和自动化领域的高速、低功耗、高精度数据采集和控制系统,以及配电和自动化领域的高速保护系统。通过管脚兼容的16位ADCDAC器件,例如MAX11166MAX5316,也可测试16位数据采集系统。

 

MAXREFDES74#参考设计的特性包括:

  • 电源和数据隔离
  • 灵活、可配置的反相或同相输入方法
  • 单极性或双极性输入(ADC)和输出(DAC)

MAX11156

  • 18位分辨率,无失码
  • 信噪比:94.4dB
  • 总谐波失真:-107dB @ 1kHz
  • 带缓冲的内部或外部电压基准输入
  • 内部基准的温度系数为-6ppm/°C(典型值)
  • 5V单电源供电
  • 真正的双极性±5V输入范围

MAX5318

  • 18位分辨率,无失码
  • 高精度±2 LSB INL(最大值)
  • 3µs稳定时间
  • 用户可编程失调和增益校准
  • ±0.5ppm/°C(典型值)偏移和增益漂移(全部温度范围)
  • 加载/感应输出
  • 50MHz SPI兼容接口,1.8V至5.5V逻辑电平

  • 5944fig00

    5944fig00

  • 5944fig01

    5944fig01

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设计,建造,测试

图中的电路板已完全组装并经过测试。

 

细节部分

细节部分

Detailed Description

The block diagram of the MAXREFDES74# board is shown in Figure 1.


Figure 1. MAXREFDES74# block diagram.

The analog front-end consists of two user-selectable MAX9632 op amps, followed by the MAX11156. The op amps can be configured as inverting or noninverting amplifiers by jumper selectors. Both op amps work as anti-aliasing lowpass filters (LPF) and can be daisy-chained to create a second-order LPF.

The output of the MAX5318 DAC can also be configured as a positive or negative single-ended output, or as a true differential output through three MAX9632 op amps. The DAC output can also be shifted up to double the output level to 2 x VREF.

The voltage reference (VREF) for both the ADC and DAC comes from the selectable reference sources, which include the MAX6126, with 3ppm/°C, 0.02% initial accuracy VREF in an 8-pin SO package, and the MAX6070, with 6ppm/°C, 0.04% initial accuracy VREF in a 6-pin SOT23 package. The MAX11156 can use an internal VREF (default operation) or one of the external references.

The shunt positions for major ADC configurations are shown in Table 1 and Figure 2, and for the DAC output in Table 2, and a VREF connection in Table 3.

Table 1. ADC Input Configuration

CONFIG # ADC INPUT CONFIGURATION INPUT CONNECTORS SHUNT POSITIONS
1 Noninverting, single-ended, second-order LPF (default) CON3: AIN0+ or (TP2 and TP8): AIN0+ and AGND J28: 1-2
J29: 1-2 and 3-4
J32: 5-6 and 3-4
J10: 1-2 and 9-10
2 Noninverting, differential, second-order LPF CON3 (TP2): AIN0+
CON2 (TP1): AIN0-
J28: Open
J29: 1-2
J32: 5-6 and 3-4
J10: 1-2 and 9-10
3 Inverting, single-ended, second-order LPF CON2: AIN0
or (TP1 and TP8): AIN0 and AGND
J28: 3-4
J29: 3-4
J32: 1-2 and 7-8
J10: 1-2 and 9-10
4 Inverting, differential, second-order LPF CON2 (TP1): AIN0-
CON3 (TP2): AIN0+
J28: Open
J29: 3-4
J32: 1-2 and 7-8
J10: 1-2 and 9-10
5 Noninverting, single-ended, first-order LPF CON5: AIN1
or (TP7 and TP15): AIN1 and AGND
J29: 1-2
J32: 3-4 and 7-8
J10: 1-2 and 9-10
6 Differential, first-order LPF CON5 (TP7): AIN1+
CON4 (TP10): AIN1-
J29: Open
J32: 3-4 and 7-8
J10: 1-2 and 9-10
7 Inverting, single-ended, first-order LPF CON4: AIN1 or (TP10 and TP15): AIN1 and AGND J29: 3-4
J32: 1-2 and 7-8
J10: 1-2 and 9-10
8 DAC noninverting, single-ended Use the on-board MAX5318 as input source* J10: 3-4 and 9-10
J9: 1-2
J5: 1-2
J18: 1-2
9 DAC inverting, single-ended Use the on-board MAX5318 as input source* J10: 5-6 and 9-10
J9: 1-2
J5: 1-2
J18: 1-2
  DAC differential Use the on-board MAX5318 as input source* J10: 3-4
Jump wire J10: 5-10


*DAC output configuration must be compliant with the ADC input range.

 

Table 2. DAC Output Configuration

CONFIG # DAC OUTPUT SHUNT POSITIONS OUTPUT CONNECTORS
10 Single ended, 0 to 3 x VREF J9: 1-2
J5: 1-2
J18: 1-2
CON11: DAC_OUT+
or (TP46 and TP41): DAC_OUT+ and AGND
11 Single ended, 0 to -3 x VREF J9: 1-2
J5: 1-2
J18: 1-2
CON10: DAC_OUT-
or (TP18 and TP17): DAC_OUT- and AGND
12 Differential, - 3 x VREF to
3 x VREF
J9: 1-2
J5: 1-2
J18: 1-2
CON11 (TP46): DAC_OUT+
CON10 (TP18): DAC_OUT-
13 Single ended, -1.5 x VREF to 1.5 x VREF (default) J9: 3-4
J5: 1-2
J18: 1-2
CON11: DAC_OUT+
or (TP46 and TP41): DAC_OUT+ and AGND


Note: Alternate connections are shown in parentheses.

 

Table 3. VREF Connection

CONFIG # VREF SHUNT POSITIONS FOR ADC SHUNT POSITIONS FOR DAC
14 Internal J13: open (default)
15 External U11 (MAX6126) J13: 2-3 J7: 2-3 (default)
16 External U12 (MAX6070) J13: 1-2 J7: 1-2

 

Default shunt positions.
Figure 2. Default shunt positions.

Power Supply

The MAXREFDES74# board receives power from a single DC source of 15V to 20V, 300mA through a J1 power jack. The MAX13256, H-bridge driver and transformer create an additional negative rail for +20V and -20V. The power is then rectified and regulated down to a +15V and -15V supplies for the op amps, as well as into +5V VDD and 3.3V VDDIO for VREF, ADC, and DAC. See the MAXREFDES74# schematic for details. Specific voltages may be connected to the board for each rail, see Table 4 for corresponding shunt positions.

Table 4. Power Supply to the Board

POWER INPUT CONNECTORS SHUNT POSITIONS
Single +15V to +20V input from a wall adapter (default) J1 J30: 1-2 Enable U1
J15: 3-4
J16: 3-4
J17: 3-4
J24: 5-6
An external ±20V TP35 (+20V)
TP30 (-20V)
TP36 (Common 0V)
J30: 2-3 Disable U1
J15: 1-2
J16: 1-2
J17: 3-4
J24: 5-6
An external ±15V TP9 (+15V)
TP23 (-15V)
TP22 (Common 0V)
J30: 2-3 Disable U1
J15: 1-2
J16: 1-2
J17: 1-2
J24: 3-4

Mezzanine Card Operation with ZedBoard

The MAXREFDES74# board is connected to the ZedBoard through a low-pin-count FMC CON1 connector. The ZedBoard should be connected to a PC through an Ethernet port, which allows the GUI to perform different operations with full control over mezzanine card functions.

Quick Start Guide

Required Equipment

  • MAXREFDES74#, 18-bit precision data acquisition board, with +15V, 1A AC-DC wall adapter or +15V DC power supply
  • ZedBoard (Part Number: AES-Z7EV-7Z020-G) with +12V AC-DC wall adapter and SD card
  • PC with Windows® 7 or later operating system
  • Ethernet cable
  • High-performance signal generator (e.g., Audio Precision 2700 series)

Procedure

The MAXREFDES74# board is fully assembled and tested. Follow the steps below to verify board operation:

  1. Download the latest version of the MAXREFDES74# Software GUI and MAXREFDES74# Zedboard firmware. Save the firmware and software to a temporary folder and uncompress the zip files. Store the firmware file to an SD card.
  2. Solder the 2-pin header on J18-3V3 of the ZedBoard. Place a shunt on the J18-3V3 header to select 3.3V I/O operation to be compatible with the MAXREFDES74# board.
  3. Connect the Ethernet cable from the PC to the ZedBoard and configure the Internet Protocol Version 4 (TCP/IPv4) properties in the local area connection to IP address 192.168.1.2 and subnet mask to 255.255.255.0.
  4. Insert the SD card with the boot file into the card slot (J12) of ZedBoard, located underneath the PCB.
  5. Verify the ZedBoard boot mode MIO2-6 jumpers are set to SD card mode as described in the Hardware User Guide for ZedBoard.
    MIO6 GND
    MIO5 3V3
    MIO4 3V3
    MIO3 GND
    MIO2 GND
  6. Turn on the power switch (SW8) of the ZedBoard to the ON position. The green power-good LED (LD13) should light and the current revision of the MAXREFDES74 firmware is displayed on the OLED (DISP1).
  7. Turn off the power to the ZedBoard.
  8. Connect the MAXREFDES74# board to the ZedBoard through the FMC connector.
  9. Apply power to the MAXREFDES74# board from a +15V wall adapter.
  10. Turn on the power to ZedBoard.
  11. Open the MAXREFDES74# GUI. The GUI automatically detects the network connection to the ZedBoard and displays a confirmation message. If no network connection is found, the GUI will go to demo mode.
  12. After the connection is established, the GUI indicates the board condition in the status bar on the bottom side of the GUI.


    Figure 3. MAXREFDES74# GUI.

  13. Verify the Clock Source, Sampling Rate, Number of Samples, and Configuration of the MAX11156 ADC, and click the Set button.
  14. Go to the DMM tab, select mV from the Display Units pulldown menu and click the Capture button. The reading of the MAX11156 ADC should display a small number in mV. That is the reading of the 0V (AGND) input. Make sure that all inputs are grounded by shunts on J28 and J29; see the ADC Input Configuration table, Table 1, and the MAXREFDES74# schematic.
  15. Go to the Scope, Histogram, and FFT tabs to verify functionality and performance of the 0V reading. Set the Sampling rate and select the Number of Samples, the Display Units, and the Average from the corresponding pulldown menu and perform a read operation by clicking the Capture button. The corresponding print screens are shown in Figure 4, Figure 5, Figure 6, and Figure 7.

    DMM tab.
    Figure 4. DMM tab.

    Scope tab.
    Figure 5. Scope tab.

    Histogram tab.
    Figure 6. Histogram tab.

    FFT tab.
    Figure 7. FFT tab.

  16. Place a J26 shunt and repeat the performance of the VREF/2 reading.
  17. Apply a 10kHz sine wave from an external source, e.g. Audio Precision 2700, to CON3 (AIN0+). Synchronize the external source with the MAXREFDES74# ADC by connecting CON9 (SYNC_CLK_OUT) to the REF IN input for coherent sampling. In the ADC Configuration tab, check the Sync-Out CLK (10MHz) selection box to enable the 10MHz clock output from the ZedBoard and click the Set button. Then go to the FFT tab, select Sampling Rate, Number of Samples, put desired signal frequency in the Input Signal (Hz) pulldown menu and then click the Calculate button. The GUI will calculate the coherent input signal frequency based on the coherent sampling equation. The user will then enter the adjusted signal frequency, shown in the Adjusted (Hz) box, into the external function generator. Then click the Capture button in the FFT tab.

    Coherent sampling of a 10kHz sine wave.
    Figure 8. Coherent sampling of a 10kHz sine wave.

    Coherent sampling of a 1kHz sine wave.
    Figure 9. Coherent sampling of a 1kHz sine wave.

DAC Output Set Up

  1. Go to the DAC configuration tab. Type in the desired DAC VOUT into the DIN (V) box and click the Set button. The software will update the DIN, OFFSET, and GAIN registers to reflect the user-desired voltage. Use an external voltmeter to check the actual DAC output on TP54, TP46, and TP18 referenced to AGND.
  2. Note: The DAC output on TP54 is in the range from 0V to VREF (4.096V), but on TP46 it can be from -1.5 x VREF (-6.1V) to 3 x VREF (+12.3V), and on TP18 from +6.1V to -12.3V, see Table 2. Alternatively, the DAC code can be entered in hex format in the DIN box and set by clicking the Write button.

  3. The Function Generation tab allows the user to generate predefined types of signals, such as sine, square, triangle, sawtooth, or arbitrary waveforms by selecting one from the Signal Type pulldown menu. The user can enter the desired Number of Samples, the DAC Update Rate, and the Signal Frequency, and then press the Calculate button. The software will adjust the DAC update rate and calculate the adjusted signal frequency. The user also needs to adjust the Amplitude and the Offset parameter of the desired waveform.
  4. By pressing the Generate button, the software calculates the necessary points and creates a lookup table (LUT) in the ZedBoard FPGA’s RAM. FPGA will loop around the LUT to generate a continuous waveform. Use an oscilloscope to check the output waveform. The output can be disabled by clicking on the Stop button.

DAC–ADC Closed-Loop Operation

The user can generate a waveform produced by the MAX5318 DAC and analyze it using the on-board MAX11156 ADC, since the DAC and ADC work independently from each other.

  1. Go to the Function Generator tab and generate the desired waveform, see the DAC Output Set Up for detail. Make sure that the amplitude and the offset meet the ADC input requirements.
  2. Set J19 shunts in position 3-4 and 9-10. The DAC_OUT+ signal is connected to the AINP input of the ADC.
  3. Go to the ADC Configuration tab and set the desired configuration for the ADC. Then go to the Scope tab, select the Sampling Rate, the Number of Samples, the Display Units, and the Average factor from the corresponding pulldown menu, and click the Capture button. The waveform will be captured and displayed in a scope window. Use the zoom-in feature to see the waveform.

Scope of the sine wave in closed-loop operation.
Figure 10. Scope of the sine wave in closed-loop operation.

Windows is a registered trademark and registered service mark of Microsoft Corporation.
Xilinx is a registered trademark and registered service mark of Xilinx, Inc.
ZedBoard is a trademark of ZedBoard.org.
Zynq is a registered trademark of Xilinx, Inc.

Maxim设备 (9)

器件号 名称 产品线 购买 设计套件和评估模块
MAX11156 18位、500ksps、内置基准的±5V SAR ADC,采用TDFN封装 模/数转换器(ADC) 立即购买 设计套件
MAX15006 40V、超低静态电流线性稳压器,6引脚TDFN/8引脚SO封装 线性稳压器 立即购买 设计套件
MAX9632 36V、高精度、低噪声宽带放大器 放大器 立即购买 设计套件
MAX6070 低噪声、高精度系列电压基准 电压基准 立即购买 设计套件
MAX5318 SPI接口、18位、高精度、电压输出DAC,提供数字增益、偏压控制 数/模转换器(DAC) 立即购买 设计套件
MAX14850 六通道数字隔离器 隔离IC 立即购买 设计套件
MAX8719 高压、低功耗线性稳压器,用于笔记本电脑 线性稳压器 立即购买 设计套件
MAX664 Dual Mode™、5V可编程的、微功耗稳压器 线性稳压器 立即购买 设计套件
MAX13256 36V H桥变压器驱动器,用于隔离电源设计 隔离电源 立即购买 设计套件

Maxim设备 (9)

器件号 产品线
模/数转换器(ADC)
18位、500ksps、内置基准的±5V SAR ADC,采用TDFN封装
线性稳压器
40V、超低静态电流线性稳压器,6引脚TDFN/8引脚SO封装
放大器
36V、高精度、低噪声宽带放大器
电压基准
低噪声、高精度系列电压基准
数/模转换器(DAC)
SPI接口、18位、高精度、电压输出DAC,提供数字增益、偏压控制
隔离IC
六通道数字隔离器
线性稳压器
高压、低功耗线性稳压器,用于笔记本电脑
线性稳压器
Dual Mode™、5V可编程的、微功耗稳压器
隔离电源
36V H桥变压器驱动器,用于隔离电源设计

设计资料 (6)

标题 类型 尺寸 日期
maxrefdes74_gui ZIP 4MB 2019-07-09
maxrefdes74_firmware ZIP 346KB 2019-07-09
rd74v01_00 ZIP 6MB 2019-07-09
maxrefdes74_sch_ra PDF 995KB 2019-07-09
reggio_rev3-Gerbers.bin PDF 219KB 2019-07-09
maxrefdes74_bom_ra PDF 17KB 2019-07-09
日期 类型
2019-07-09

maxrefdes74_gui

(ZIP, 4MB)

2019-07-09

maxrefdes74_firmware

(ZIP, 346KB)

2019-07-09

rd74v01_00

(ZIP, 6MB)

2019-07-09

maxrefdes74_sch_ra

(PDF, 995KB)

2019-07-09

reggio_rev3-Gerbers.bin

(PDF, 219KB)

2019-07-09

maxrefdes74_bom_ra

(PDF, 17KB)

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