DS2154

Enhanced E1 Single Chip Transceiver


Description

The DS2154 is a second-generation line interface unit for E1 lines. It is pin- and software-compatible with the first-generation DS2153Q and function- and pin-compatible with the DS2152, its T1 counterpart. The DS2154 retains all features of the DS2153Q adding crystalless jitter attenuation, additional hardware signaling, a full HDLC controller for the FDL layer with 16-byte buffers, and the option for nonmultiplexed bus operation.

The DS2154 meets E1 specifications, including ETS 300 011, 300 233, 300 166, TBR 12, and TBR 13 and ITU G.703, G.704, G.706, G.823, and I.431.

Through the parallel port, the user can quickly access the 8-bit internal registers and configure the DS2154 to the application under processor control.
DS2154: Pin Configuration DS2154: Pin Configuration Enlarge+

Key Features

  • Complete E1(CEPT) PCV-30/ISDN-PRI transceiver
  • Long- and short-haul line eterface for clock/data recovery and waveshaping
  • 32-bit or 128-bit crystalless jitter attenuator
  • Generates line buildouts for both 120Ω and 75Ω lines
  • Frames to FAS, CAS, and CRC4 formats
  • Dual elastic buffers connect to asynchronous backplanes up to 8.192MHz
  • 8-bit parallel control port can be used directly
  • Parallel port can also be muxed or nonmuxed to bus
  • Extracts/inserts CAS signaling
  • Detects/generates remote and AIS alarms
  • Progammable output clocks for Fractional E1, H0, and H12
  • Independent transmit/receive functions
  • Full access to both Si and Sa bits aligned with CRC multiframe
  • Four testing loopbacks
  • Large error counter for bipolar and code, CRC4 code/word, FAS, and E-bits
  • Pin-compatible with DS2152 T1 Transceiver
  • Operating ranges:
    • 5V, low-power CMOS
    • 0°C to +70°C (DS2154L)
    • -40°C to +85°C (DS2154LN)

Technical Documents

App Note 3479 DS2154 – Migrating from Revision A2 to D1
App Note 3208 Elastic Store Operation
App Note 561 Tech Brief 7: DS2152 and DS2154 8MHz System Clock Operation
App Note 405 Power-Fault Protection Layout
App Note 393 E1 Operation of Dallas Semiconductor Framers and SCTs
App Note 370 Using RCLK in a BITS/SSU Application
App Note 361 DS21354/DS21554 vs. DS2154 Single Chip Transceivers
App Note 355 DS21Q4x, DS215x, and DS21x5y Test Registers
App Note 354 DS2152, DS2154 Clock Map
App Note 352 General network interface design criteria for the DS2153 and DS2154
App Note 351 T1/E1 and T3/E3 Transformer Selection Guide
App Note 348 DS2154L vs. DS2153Q
App Note 346 Converting the DS2152/DS2154 Demo Kits
App Note 342 T1/E1 Framer Initialization and Programming
App Note 341 DS2151, DS2153 Device Identification
App Note 340 DS2153 Programming, ETS 300-011 Remote Alarm Generation
App Note 336 Transparent Operation on T1, E1 Framers and Transceivers
App Note 325 DS2151, DS2152, DS2153, DS2154 Dallas Single Chip Transceiver Crystal Selection Guide
App Note 324 T1/E1 Network Interface Design
App Note 323 DS2151, DS2152, DS2153, DS2154 T1/E1 Line Monitor
App Note 322 DS2153, DS2154 Selectable 120 and 75Ω E1 Interface
App Note 321 DS2152, DS2154 Interfacing to the IGT ALL1 SAR (WAC-021-C)
App Note 319 DS2152, DS2154, DS21x5Y, and DS2155 Interfacing to the MC68360 (QUICC32)
App Note 317 DS2152, DS2154 Interfacing to the Siemens PXB4220
App Note 309 Interfacing to the Fractional T1 and E1
App Note 307 DS2152, DS2154, DS2151, DS2153, DS21X5Y and DS2155 Three Channel Drop and Insert
App Note 301 Legacy T1/E1 8MHz Backplane Operation

Quality and Environmental Data

Product Reliability Reports: DS2154.pdf 
Lead-Free Package Tin (Sn) Whisker Reports
 

Related Resources

Type ID PDF Title
App Note 3479 DS2154 – Migrating from Revision A2 to D1
App Note 3208 Elastic Store Operation
App Note 561 Tech Brief 7: DS2152 and DS2154 8MHz System Clock Operation
App Note 405 Power-Fault Protection Layout
App Note 393 E1 Operation of Dallas Semiconductor Framers and SCTs
App Note 370 Using RCLK in a BITS/SSU Application
App Note 361 DS21354/DS21554 vs. DS2154 Single Chip Transceivers
App Note 355 DS21Q4x, DS215x, and DS21x5y Test Registers
App Note 354 DS2152, DS2154 Clock Map
App Note 352 General network interface design criteria for the DS2153 and DS2154
App Note 351 T1/E1 and T3/E3 Transformer Selection Guide
App Note 348 DS2154L vs. DS2153Q
App Note 346 Converting the DS2152/DS2154 Demo Kits
App Note 342 T1/E1 Framer Initialization and Programming
App Note 341 DS2151, DS2153 Device Identification
App Note 340 DS2153 Programming, ETS 300-011 Remote Alarm Generation
App Note 336 Transparent Operation on T1, E1 Framers and Transceivers
App Note 325 DS2151, DS2152, DS2153, DS2154 Dallas Single Chip Transceiver Crystal Selection Guide
App Note 324 T1/E1 Network Interface Design
App Note 323 DS2151, DS2152, DS2153, DS2154 T1/E1 Line Monitor
App Note 322 DS2153, DS2154 Selectable 120 and 75Ω E1 Interface
App Note 321 DS2152, DS2154 Interfacing to the IGT ALL1 SAR (WAC-021-C)
App Note 319 DS2152, DS2154, DS21x5Y, and DS2155 Interfacing to the MC68360 (QUICC32)
App Note 317 DS2152, DS2154 Interfacing to the Siemens PXB4220
App Note 309 Interfacing to the Fractional T1 and E1
App Note 307 DS2152, DS2154, DS2151, DS2153, DS21X5Y and DS2155 Three Channel Drop and Insert
App Note 301 Legacy T1/E1 8MHz Backplane Operation