MAX107

Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier


Description

The MAX107 is a dual, 6-bit, analog-to-digital converter (ADC) designed to allow fast and precise digitizing of in-phase (I) and quadrature (Q) baseband signals. The MAX107 converts the analog signals of both I and Q components to digital outputs at 400Msps while achieving a signal-to-noise ratio (SNR) of typically 37dB with an input frequency of 125MHz, and an integral nonlinearity (INL) and differential nonlinearity (DNL) of ±0.25 LSB. The MAX107 analog input preamplifiers feature a 400MHz, -0.5dB, and a 1.5GHz, -3dB analog input bandwidth. Matching channel-to-channel performance is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees phase. Dynamic performance is 36.7dB signal-to-noise plus distortion (SINAD) with a 125MHz analog input signal and a sampling speed of 400MHz. A fully differential comparator design and encoding circuits reduce out-of-sequence errors, and ensure excellent metastable performance of only one error per 1016 clock cycles.

In addition, the MAX107 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two's complement format. The MAX107 operates from a +5V analog supply and the LVDS output ports operate at +3.3V. The data converter's typical power dissipation is 2.6W. The device is packaged in an 80-pin, TQFP package with exposed paddle, and is specified for the extended (-40°C to +85°C) temperature range. For a higher-speed, 800Msps version of the MAX107, please refer to the MAX105 data sheet.
MAX107: Block Diagram MAX107: Block Diagram Enlarge+

Key Features

  • Two Matched 6-Bit, 400Msps ADCs
  • Excellent Dynamic Performance
    • 36.7dB SINAD at fIN ≈ 125MHz and
    • fCLK ≈ 400MHz
  • Typical INL and DNL: ±0.25LSB
  • Channel-to-Channel Phase Matching: ±0.2°
  • Channel-to-Channel Gain Matching: ±0.04dB
  • 6:12 Demultiplexer reduces the Data Rates to 200MHz
  • Low Error Rate: 1016 Metastable States at 400Msps
  • LVDS Digital Outputs in Two's Complement Format

Applications/Uses

  • Communication Systems
  • Test Instrumentation
  • VSAT Receivers
  • Wireless Local Area Networks (WLANs)
Part Number Input Chan. Resolution
(bits)
Sample Rate
(Msps)
AC Specs
(MHz)
SFDR
(dBc)
ENOB
(bits)
SINAD
(dB)
SNR
(dB)
THD
(dB)
DNL
(±LSB)
INL
(±LSB)
Full Pwr. BW
(MHz)
ICC
(mA)
Data Bus Interface Budgetary
Price
max ≥ @ fIN min min min typ See Notes
MAX107  2 6 400 125 51 5.9 36.7 37 -49.5 0.25 0.2 400 650
µP/8
Demuxed
LVPECL
$29.25 @1k
See All High-Speed ADCs (> 5Msps) (73)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific and version-specific prices and delivery, please see the price and availability page or contact an authorized distributor.

Technical Documents

Tutorial 800 Design a Low-Jitter Clock for High-Speed Data Converters
App Note 642 ADC Captures 1Gsps
Tutorial 283 INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs)

Quality and Environmental Data

Request Reliability Report for: MAX107 
Lead-Free Package Tin (Sn) Whisker Reports
 

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