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MAX11040K, MAX11060

24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs

Sigma-Delta ADCs Cascadable Up to 32 Simultaneous Channels
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Active: In Production.

Description

The MAX11040K/MAX11060 are 24-/16-bit, 4-channel, simultaneous-sampling, sigma-delta analog-to-digital converters (ADCs). The devices allow simultaneous sampling of as many as 32 channels using a built-in cascade feature to synchronize as many as eight devices. The serial interface of the devices allows reading data from all the cascaded devices using a single command. Four modulators simultaneously convert each fully differential analog input with a programmable data output rate ranging from 0.25ksps to 64ksps. The devices achieve 106dB SNR at 16ksps and 117dB SNR at 1ksps (MAX11040K). The devices operate from a single +3V supply. The differential analog input range is ±2.2V when using the internal reference; an external reference is optional. Each input is overvoltage protected up to ±6V without damage. The devices use an internal crystal oscillator or an external source for clock.
The devices are compatible with SPI, QSPI™, MICROWIRE®, and DSP-compatible 4-wire serial interfaces. An on-board interface logic allows one serial interface (with a single chip select) to control up to eight cascaded devices or 32 simultaneous sampling analog input channels.
The devices are ideally suited for power-management systems. Each channel includes an adjustable sampling phase enabling internal compensation for phase shift due to external dividers, transformers, or filters at the inputs. The output data rate is adjustable with a 0.065% resolution (at 16ksps or below) to track the varying frequency of a periodic input. An active-low SYNC input allows periodic alignment of the conversion timing of multiple devices with a remote timing source.
The devices are available in a 38-pin TSSOP package specified over the -40°C to +105°C industrial temperature range.

Data Sheet

Download this datasheet in PDF formatDownload Rev 3 (PDF, 585kB)
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An evaluation board is available: MAX11040KDBEVKIT, MAX11040KEVKIT

Key Features

  • Four Fully Differential Simultaneously Sampled Channels
  • Cascadable for Up to 32 Channels of Simultaneous Sampling
  • 106dB (MAX11040K) SNR at 16ksps
  • 117dB (MAX11040K) SNR at 1ksps
  • 0.25% Error Over a 1000:1 Dynamic Range, Processed Over 16.7ms (MAX11040K)
  • ±2.2V Full-Scale Input Range
  • ±6V Overvoltage Protected Inputs
  • Internal Crystal Oscillator
  • 2.5V, 50ppm/°C Internal Reference or External Reference
  • Programmable Output Data Rate
    • 0.25ksps to 64ksps Range
    • 0.065% Resolution
  • Programmable Sampling Phase
      0 to 333µs Delay in 1.33µs Steps
  • SPI-/QSPI-/MICROWIRE-/DSP-Compatible 4-Wire Serial Interface
  • Cascadable Interface Allows Control of Up to Eight Devices with a Single CS Signal
  • 3.0V to 3.6V Analog Supply Voltage
  • 2.7V to VAVDD Digital Supply Voltage
  • 38-Pin TSSOP Package
 

Applications/Uses

  • Industrial Data-Acquisition Systems
  • Medical Instrumentation
  • Multiphase Power Systems
  • Power-Protection Relay Equipment
   

Key Specifications:

Precision ADCs (< 5Msps)
Part Number Resolution
(bits)
Input Chan. Conv. Rate
(ksps)
ADC Architecture Data Bus Diff/S.E. Input Internal VREF
(V)
External VREF
(V)
External VREF
(V)
Bipolar VIN
(±V)
SNR
(dB)
SINAD
(dB)
Budgetary
Price
ADC max nominal min max max See Notes
MAX11060  16 4 64 Sigma-Delta SPI Diff. Only 2.5 2.3 2.7 2.2 94.5 94 $5.60 @1k
MAX11040K  24 Both 106 98 $13.82 @1k
See All Precision ADCs (< 5Msps) (456)

Pricing Notes:

This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific and version-specific prices and delivery, please see the price and availability page or contact an authorized distributor.



Diagram

MAX11040K, MAX11060: Functional Diagram
Functional Diagram

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Information Index

Document Ref.: 19-5741 Rev 3; 2012-10-16
This page last modified: 2012-10-16