DS31256

256-Channel, High-Throughput HDLC Controller

256-Channel HDLC Controller Capable of Handling Up to 60 T1 or 64 E1 Data Streams or Two T3 Data Streams
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Status Explanations for product status codes

Part Number Status
DS31256 This product is Not Recommended for New Designs.

Description

The DS31256 is a 256-channel HDLC controller that can handle up to 60 T1 or 64 E1 data streams or two T3 data streams. Each of the 16 physical ports can handle one, two, or four T1 or E1 data streams. The DS31256 is composed of the following blocks: Layer 1, HDLC processing, FIFO, DMA, PCI bus, and local bus.

There are 16 HDLC engines (one for each port) that are each capable of operating at speeds up to 8.192Mbps in channelized mode and up to 10Mbps in unchannelized mode. The DS31256 also has three fast HDLC engines that only reside on Ports 0, 1, and 2. They are capable of operating at speeds up to 52Mbps.

Data Sheet

Download this datasheet in PDF formatDownload Rev 4 (PDF, 1.2MB)
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Errata DS31256 31256B2.pdf
Errata DS31256 31256A2.pdf

Key Features

  • 256 Independent, Bidirectional HDLC Channels
  • Up to 132Mbps Full-Duplex Throughput
  • Supports Up to 60 T1 or 64 E1 Data Streams
  • 16 Physical Ports (16 Tx and 16 Rx) That Can Be Independently Configured for Channelized or Unchannelized Operation
  • Three Fast (52Mbps) Ports; Other Ports Capable of Speeds Up to 10Mbps (Unchannelized)
  • Channelized Ports Can Each Handle One, Two, or Four T1 or E1 Lines
  • Per-Channel DS0 Loopbacks in Both Directions
  • Over-Subscription at the Port Level
  • Transparent Mode Supported
  • On-Board Bit Error-Rate Tester (BERT) with Automatic Error Insertion Capability
  • BERT Function Can Be Assigned to Any HDLC Channel or Any Port
  • Large 16kB FIFO in Both Receive and Transmit Directions
  • Efficient Scatter/Gather DMA Maximizes Memory Efficiency
  • Receive Data Packets are Time-Stamped
  • Transmit Packet Priority Setting
  • V.54 Loopback Code Detector
  • Local Bus Allows for PCI Bridging or Local Access
  • Intel or Motorola Bus Signals Supported
  • Backward Compatibility with DS3134
  • 33MHz 32-Bit PCI (V2.1) Interface
  • 3.3V Low-Power CMOS with 5V Tolerant I/O
  • JTAG Support IEEE 1149.1
  • 256-Pin Plastic BGA (27mm x 27mm)


Features continued on page 6 of the PDF data sheet.
 

Applications/Uses

  • Channelized and Clear Channel (Unchannelized) T1/E1 and T3/E3
  • High-Density Frame-Relay Access
  • High-Density V.35
  • Routers with Multilink PPP Support
  • SONET/SDH EOC/ECC Termination
  • Triple HSSI
  • xDSL Access Multiplexers (DSLAMs)
   

Diagram

DS31256: Block Diagram
Block Diagram

More Information

New Product Press Release   2002-11-21 ]

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Rev 4; 2006-01-27
This page last modified: 2009-10-13