DS21Q42

Enhanced Quad T1 Framer

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Description

The DS21Q42 is an enhanced version of the DS21Q41B quad T1 framer. The DS21Q42 contains four framers that are configured and read through a common microprocessor-compatible parallel port. Each framer consists of a receive framer, receive elastic store, transmit formatter, and transmit elastic store. All four framers in the DS21Q42 are totally independent; they do not share a common framing synchronizer. The transmit and receive sides of each framer are also totally independent. The dual two-frame elastic stores contained in each of the four framers can be independently enabled and disabled as required. The device fully meets all of the latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90), AT&T TR54016, and ITU G.704 and G.706.

Data Sheet

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Key Features

  • Four T1 DS1/ISDN-PRI/J1 framing transceivers
  • All four framers are fully independent
  • Each of the four framers contain dual twoframe elastic-store slip buffers that can connect to asynchronous backplanes up to 8.192MHz
  • 8-bit parallel control port that can be used directly on either multiplexed or nonmultiplexed buses (Intel or Motorola)
  • Programmable output clocks for Fractional T1
  • Fully independent transmit and receive functionality
  • Integral HDLC controller with 64-byte buffers configurable for FDL or DS0 operation
  • Generates and detects in-band loop codes from 1 to 8 bits in length including CSU loop codes
  • Pin compatible with DS21Q44 E1 enhanced quad E1 framer
  • 3.3V supply with 5V tolerant I/O; low-power CMOS
  • Available in 128-pin TQFP package
  • IEEE 1149.1 support
   
   

Diagram

DS21Q42: Functional Diagram
Functional Diagram

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Rev 1; 2002-06-26
This page last modified: 2009-10-22