DS21354, DS21554

3.3V/5V E1 Single Chip Transceivers (SCT)

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Status Explanations for product status codes

Part Number Status
DS21354 This product is Not Recommended for New Designs. Some versions may be No Longer Available or being discontinued and subject to Last Time Buy, after which new orders can not be placed. See Ordering Information for details.
DS21554 Active: In Production. See Ordering Information for details.

Description

The DS21354/DS21554 single-chip transceivers (SCTs) contain all the necessary functions to connect to E1 lines. The devices are upward-compatible versions of the DS2153 and DS2154 SCTs. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. Both devices automatically adjust to E1 22AWG (0.6mm) twistedpair cables from 0 to over 2km in length. They can generate the necessary G.703 waveshapes for both 75Ω coax and 120Ω twisted cables. The on-board jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa-bit information. The on-board HDLC controller can be used for Sa-bit links or DS0s. The devices contain a set of internal registers that the user can access to control the operation of the units. Quick access through the parallel control port allows a single controller to handle many E1 lines. The devices fully meet all the latest E1 specifications, including ITU-T G.703, G.704, G.706, G.823, G.732, and I.431, ETS 300 011, 300 233, and 300 166, as well as CTR12 and CTR4.

Data Sheet

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Errata DS21554 21554_Q554A4.pdf
Errata DS21354 21354_Q354A4.pdf
Errata DS21354 21354_Q354B2.pdf
Errata DS21354 21354_Q354C1.pdf
Errata DS21554 21554_Q554B1.pdf
Errata DS21554 21554_Q554C1.pdf

Key Features

  • Complete E1 (CEPT) PCM-30/ISDN-PRI Transceiver Functionality
  • On-Board Long- and Short-Haul Line Interface for Clock/Data Recovery and Waveshaping
  • 32-Bit or 128-Bit Crystal-Less Jitter Attenuator
  • Frames to FAS, CAS, CCS, and CRC4 Formats
  • Integral HDLC Controller with 64-Byte Buffers Configurable for Sa Bits, DS0, or Sub-DS0 Operation
  • Dual Two-Frame Elastic Store Slip Buffers that can Connect to Asynchronous Backplanes up to 8.192MHz
  • Interleaving PCM Bus Operation
  • 8-Bit Parallel Control Port that can be used Directly on Either Multiplexed or Nonmultiplexed Buses (Intel or Motorola)
  • Extracts and Inserts CAS Signaling
  • Detects and Generates Remote and AIS Alarms
  • Programmable Output Clocks for Fractional E1, H0, and H12 Applications
  • Fully Independent Transmit and Receive Functionality
  • Full Access to Si and Sa Bits Aligned with CRC-4 Multiframe
  • Four Separate Loopback Functions for Testing Functions
  • Large Counters for Bipolar and Code Violations, CRC4 Codeword Errors, FAS Word Errors, and E Bits
  • IEEE 1149.1 JTAG-Boundary Scan Architecture
  • Pin Compatible with DS2154/52/352/552 SCTs
  • 3.3V (DS21354) or 5V (DS21554) Supply; Low- Power CMOS
  • 100-pin LQFP package (14mm x 14mm)
   
   

Key Specifications:

T/E Carrier & Packetized Products
Part Number Transmission Standard Functions Channels VSUPPLY
(V)
Budgetary
Price
See Notes
DS21354  E1 Framer + LIU 1 3.3 $16.48 @1k
DS21554  5
See All T/E Carrier & Packetized Products (88)

Pricing Notes:

This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific and version-specific prices and delivery, please see the price and availability page or contact an authorized distributor.



Diagram

DS21354, DS21554: Pin Configuration
Pin Configuration

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Rev 1; 2004-02-10
This page last modified: 2009-10-23