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A Triple-Output ±5% Regulated High Efficiency POE (Power over Ethernet) Supply
Dec 26, 2004
Abstract: This note describes a triple-output, high efficiency, POE (Power over Ethernet) power supply with synchronous rectification. The supply has ±5% regulation an all outputs and meets all the IEEE802.3af requirements. The topology for the dc-dc converter is a continuous current flyback. The switching frequency for the primary PWM is 275 Khz.
The maximum input power available to a POE power supply depends on the PD power classification. Maximum PD power is 12.95 watts for a class 0 PD power classification. The maximum PD power for a class 1 PD power classification is 3.85 watts. This application note describes a triple-output, 3.12 watts, high-efficiency POE power supply with ±5% regulation on all the outputs.
Utilizes an IEEE802.3af-compliant POE interface plus PWM controller in a single 16-pin SO package (MAX5941A)
Flyback topology for the power supply
Synchronous rectification on all outputs
Isolated outputs with an isolation voltage of 1500VAC
±5% regulation on all outputs
Output +3.3V at 0.2A, +2.5V at 0.6A, and +1.2V at 0.8A
Description of Power Supply Operation
Figure 1 is the circuit diagram of the triple-output POE power supply using the MAX5941A IEEE802.3af-compliant POE interface plus a current-mode PWM controller(U2). The power supply has a flyback topology with synchronous rectifiers on the 3.3V and 2.5V output, and a buck converter with synchronous rectification for the 1.2V output of the 3.3V. The circuit diagram does not include the diode bridge portion of the input section.
IEEE802.3af-Compliant POE Interface Section of the Circuit
One half of the MAX5941A IC is dedicated to the POE interface section. The DC output from the diode bridge appears across capacitor C10. Zener diode D4 prevents overvoltages at the MAX5941A. The MAX5941A's internal hot-swapMOSFET turns on at 39V and slowly charges capacitor C6 to 40V. The inrush current is limited by the controlled turn-on of the MOSFET. The PGOOD signal goes high when capacitor C6 is almost fully charged to the input voltage. R10 is the PD detection resistor and R25 is the classification resistor.
The second half of the MAX5941A is the PWM section. The PWM starts operation when power is applied to the PWM portion of the controller. Soft-start capacitor C14 slowly increases the peak primary current in the power transformer.
The PWM is a current-mode controller operating at 275kHz with an 85% maximum duty cycle. R19 is the current-sense resistor. The current-sense voltage is fed to the current-sense pin on the PWM controller, making the gate drive now available on the NDRV pin. Initial bias is provided by the internal high-voltage regulator of the input from capacitor C8 inside the MAX5941A. Once the switching starts and the voltage on the capacitor C2 exceeds 10V, then the bias power is provided by VDD and not from the input.
The NDRV output is fed to the totem-pole buffer comprised of transistors Q1 and Q3, resistors R16 and R2, capacitor C18, and diode D1. The buffer delays the drive to MOSFET Q2 so the secondary dual synchronous rectifier MOSFET U1 can be turned off as soon as the gate drive from the MAX5941A goes high. This avoids any momentary short-circuit problems at the transformer (T1) secondary when Q2 turns on.
Transformer T1 has five windings. Starting on 1 and ending on 12, the primary winding is 40 turns on an EFD 15 core with an SMD bobbin. The 17-turn primary bias winding provides primary bias power. There are three secondary windings, isolated from the primary winding to withstand 1500VAC. The secondary winding consisting of turns on pins 5 to 8 is for the 3.3V output; the windings, consisting of turns on pins 6 to 7, are for the 2.5V output. The winding on pins 4 to 9 forms the drive winding for the turn-on of the MOSFETs in U1 and is in phase with the output windings. The 3.3V and 2.5V windings are wound bifilar to maximize coupling between these windings.
The dual MOSFET U1 is used for synchronous rectification on the 3.3V and 2.5V outputs to maintain the high efficiency. The transformer (T1 pins 9,4) drive winding turns on the gates of the MOSFETs in U1. Voltage on the drive winding goes positive when the primary MOSFET Q2 is turned off and simultaneously Q6 is turned off by T2. As soon as the MAX5941's NDRV pin goes high, the gate drive transformer T2 turns on the gate turn-off MOSFET Q6, which turns off the dual MOSFETs in U1. In this way synchronous rectification is achieved on both the 3.3V and 2.5V outputs.
3.3V and 2.5V Feedback Section
U3 is an IC containing an optocoupler, an error feedback amplifier, and an internal 1.24V reference. The 2.5V and the 3.3V output are fed to the error amplifier through resistors R22 and R1. The feedback controller maintains the voltage across R24 at 1.24V because the internal 1.24V reference voltage is fed to the positive input of the internal error amplifier in U3. The value of the resistors R1 and R22 is such that almost half of the current flowing into R24 comes from the 3.3V and the other half comes from the 2.5V. With this process and with synchronous rectification, a regulation better than ± 5% is achieved on both the 3.3V and 2.5V outputs. The other components in the feedback section are C11, C15, R13, R14 and R21. Resistor R21 maintains a minimum current that flows into the error amplifier output when the optocoupler is conducting.
1.2V Output Section
The 1.2V output is obtained from the 3.3V by a buck regulator with synchronous rectifiers. U4 (MAX8505) is a buck regulator PWM IC containing both the controller and the MOSFETs required for synchronous rectification. The DC-regulated 1.2V output is available across capacitors C20 and C21.